AN-202 Datasheet, PDF (1/6 Pages) Exar Corporation – USB UART BOARD DESIGN CONSIDERATIONS FOR USB COMPLIANCE

Application Note AN-202
Programming Z-COMM Phase Locked Loops
Nomenclature
Z-COMM has three models of Phase Locked Loops available, each using either the National Semiconductor or
the Analog Devices PLL synthesizer chip.
PSNxxxxx:
PSAxxxxx:
PCAxxxxx:
Phase Locked Loop, Standard Package (0.6” x 0.9”), National Semiconductor.
Phase Locked Loop, Standard Package, Analog Devices.
Phase Locked Loop, Compact Package (0.5” x 0.5”), Analog Devices.
This application note will cover the programming techniques of each of Z-COMM’s Phase Locked Loops.
Compact Package Pin Description
P1
RF Output
P2
Reference Oscillator Input
P3
Clock
P4
Data
P5
Load Enable
P6
Lock Detect
P7
Vcc
P8
No Connection
P9
No Connection
P10-12 Ground
Standard Package Pin Description
P1
*P1 RF Output
P2
P2-4 Ground
P3
P5
Reference Oscillator Input
P4
P7
Clock
P5
P8
Data
P6
P10 Load Enable
P7
P12 Lock Detect
P8
P13 Vcc
P9
P14-16 Ground
P10 P17 No Connection
P11-14 P18-24 Ground
*Pin out for PLL-24 Standard Package
Each of the PLL synthesizers includes the reference divider (R counter), phase detector, charge pump, and the
main divider (N counter). Z-COMM provides the completed PLL with the inclusion of the loop filter and the VCO
into the PLL module. Typically the end user supplies the crystal reference.
Does your PLL have a National Semiconductor synthesizer chip?
Z-COMM uses the LMX2306, 2316, and the 2326 PLL synthesizer chips. Please refer to the data sheet for your
PLL to find out which one is used.
National Semiconductor uses a 21-bit shift register to load data via a 3 wire connect. These correspond to the
clock, data, and load enable pins on the PLL. See figure 1.
LSB
MSB
C1 C2 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19
Figure 1. 21-bit shift register.
The data stream is shifted into the data input on the rising edge of the clock, most significant bit first. Then the
data is transferred from the shift register to one of four latches on the rising edge of load enable (LE).
The first 2 bits of the register are control bits and are used to program the R counter, N counter, function latch
(Fast Lock modes), or initialization. Table 1 shows the bit configuration for the 4 states.
Control
C1 C2
0
0
1
0
0
1
1
1
DATA Location
R Counter
N Counter
Function Latch
Initialization
One now needs to determine the frequencies and mode of operation. The
National PLL synthesizer provides 5 modes of operation, 4 Fast Lock modes,
and a normal operation mode. All of Z-COMM PLLs with a National chip are
built to run in normal mode only. Additional hardware in the PLL module is
required to make use of the Fast Lock modes.
Table 1.
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