AN-202 Datasheet, PDF (3/6 Pages) Exar Corporation – USB UART BOARD DESIGN CONSIDERATIONS FOR USB COMPLIANCE

Function Description
C1, C2
R1-14
R15-18
R19
Control Bits. These are configured load the R counter.
Divide ratio of the reference divider. This ratio must be: 3 ≤ R ≤ 16383.
Test modes. These bits should be zero for normal operation.
Lock Detect Precision. When this bit is a ‘1’ 5 consecutive reference cycles, instead of 3,
will be used.
N Counter
The N counter consists of 2 sub-counters, a 5-bit swallow counter, called the A counter, and a 13-bit B counter.
This section will show how to calculate the A and B counters, and set the charge pump current. Figure 4 shows
the contents of the 21-bit register to properly load in the A and the B counter for N = 1000 and charge pump
current of 1mA.
LSB
N COUNTER
MSB
C1 C2 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19
100001011111000000001
Control
Bits
Figure 4.
A Counter
B Counter
GO Bit
The main divider ratio, N is defined as:
N = Output Freq of the VCO
Compare Freq, (Step Size)
For example: 1000MHz RF output =1000 (this value must be an integer)
1000KHz Step size
National Semiconductor defines N, A, and B in the following way:
N = P * B + A; where P is the value of the prescaler. Note: For Z-COMM PLLs employing the LMX2306 chip
use “8” for the prescaler, for the LMX2316 and the LMX2326 use “32” for the prescaler.
B = div(N / P); where div(x) is defined as the integer portion.
A = N – (B * P)
Continuing our example:
B = div(1000 / 32) = div(31.25) = 31 = 0000000011111
A = 1000 – (31 * 32) = 8 = 01000
Function Description
C1, C2
N1-N5
N6- N18
N19
Control Bits. These are configured load the N counter.
A Counter. N1 is the LSB and N5 is the MSB. 0 ≤ A ≤ 31 for the LMX2316/26,
0 ≤ A ≤ 7 for the LMX2306, and A ≤ B for all chips.
B counter. N6 is the LSB and N18 is the MSB. 3 ≤ B ≤ 8191.
GO Bit. This sets the charge pump output current. “1” high 1mA, “0” low 250µA.
Please see the data sheet for your PLL to find the charge pump current setting.
A Note about Timing
The National chip has a minimum clock pulse width high and low of 50 ns, 20 MHz. This is the rate at which
data is clocked into the 21-bit shift register. When the load enable bit goes high the data is latched in.
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