MT9076B Datasheet, PDF (97/172 Pages) Zarlink Semiconductor Inc – T1/E1/J1 3.3 V Single Chip Transceiver

MT9076B
Data Sheet
Bit
Name
Functional Description
7
FEOL
Framing Bit Error Counter Overflow Latch. This bit is set when the framing bit
counter overflows. It is cleared after being read.
6
CRCOL CRC-6 Error Counter Overflow Latch. This bit is set when the crc error counter
overflows. It is cleared after being read.
5
OOFOL Out Of Frame Counter Overflow Latch. This bit is set when the out of frame counter
overflows. It is cleared after being read.
4
COFAOL Change of Frame Alignment Counter Overflow Latch. This bit is set when the
change of frame alignment counter overflows. It is cleared after being read.
3
LCVOL Line Code Violation Counter Overflow Latch. This bit is set when the line code
violation counter overflows. It is cleared after being read.
2
PRBSOL Psuedo Random Bit Sequence Error Counter Overflow Latch. This bit is set when
the PRBS error counter overflows. It is cleared after being read.
1 PRBSMFOL Psuedo Random Bit Sequence Multiframe Counter Overflow Latch. This bit is set
when the multiframe counter attached to the PRBS error counter overflows. It is cleared
after being read.
0
MFOOFOL Multiframes Out Of Sync Overflow Latch. This bit is set when the multiframes out of
sync counter overflows. It is cleared after being read.
Table 77 - Overflow Reporting Latch
(Page 4, Address 1FH) (T1)
20.1.5 Per Channel Transmit Signalling (Pages 5 and 6) (T1)
Page 05H, addresses 10000 to 11111, and page 06H addresses 10000 to 10111 contain the Transmit signaling
Control Words for DS1 channels 1 to 16 and 17 to 24 respectively. Table 78 illustrates the mapping between the
addresses of these pages and the DS1 channel numbers. Control of these bits for any one channel is through the
processor or controller port when the Per Time Slot Control bit RPSIG bit is high. Table 79 describes bit allocation
within each of these registers.
Page 5 Address:
Equivalent DS1
channel
Page 6 Address:
Equivalent DS1
channel
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
012345678
17 18 19 20 21 22 23 24 x
9 10 11 12 13 14 15
xxxxxxx
Table 78 - Pages 5 and 6 Address Mapping to DS1 Channels (T1)
97
Zarlink Semiconductor Inc.