MT9076B Datasheet, PDF (28/172 Pages) Zarlink Semiconductor Inc – T1/E1/J1 3.3 V Single Chip Transceiver

MT9076B
Data Sheet
dB
-0.5
0
-20 dB/decade
19.5
10
40
400
10 K
Frequency (Hz)
Figure 10 - TR 62411 Jitter Attenuation Curve
2.0 Clock Jitter Attenuation Modes
MT9076 has three basic jitter attenuation modes of operation, selected by the BS/LS and S/FR/Exclki control pins.
• System Bus Synchronous Mode
• Line Synchronous Mode
• Free-run mode
Depending on the mode selection above, the PLL can either attenuate transmit clock jitter or the receive clock jitter.
Table 5 shows the appropriate configuration of each control pin to achieve the appropriate mode and Jitter
attenuation capability of the MT9076.
Mode Name
BS/LS
S/FR/Exclki
Note
System Bus Synchronous
1
1
PLL locked to C4b
Line Synchronous
0
1
PLL locked to Exclk
Free-Run
x
0
PLL free - running
Table 5 - Selection of Clock Jitter Attenuation Modes using the M/S and MS/FR Pins
In System Bus Synchronous mode, pins C4b and F0b are always configured as inputs, while in the Line
Synchronous and Free-Run modes C4b and F0b are configured as outputs.
Referring to the mode names given in Table 5 the basic operation of the jitter attenuation modes are:
• In System Bus Synchronous mode an external clock is applied to C4b. The applied clock is dejittered by the
internal PLL before being used to synchronize the transmitted data. The clock extracted (with no jitter
attenuation performed) from the receive data can be monitored on pin Exclk.
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Zarlink Semiconductor Inc.