SP5768 Datasheet, PDF (8/10 Pages) Zarlink Semiconductor Inc – 3.0 GHz Low Phase Noise Frequency Synthesiser

SP5768
Application Notes
A generic set of application notes AN168 for designing
withsynthesisers such as the SP5768 has been written.
This covers aspects such as loop filter design and
decoupling. This application note is also featured in the
Media Data Book, or refer to the Zarlink Semiconductor
Internet Site http://www.zarlink.com.
Reference Source
The SP5768 offers optimal LO phase noise
performance when operated with a large step size. This
is due to the fact that the LO phase noise within the loop
bandwidth is:
( ) ^{phase comparator}
LO frequency
noise floor + 20 log phase comparator frequency
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Assuming the phase comparator noise floor is flat
irrespective of sampling frequency, this means that the
best performance will be achieved when the overall LO
to phase comparator division ratio is a minimum.
Loop Bandwidth
The majority of applications for which the SP5768 is
intended require a loop filter bandwidth of between
2kHz and10kHz.
Typically the VCO phase noise will be specified at both
1kHz and10kHz offset. It is common practice to arrange
the loop filter bandwidth such that the 1kHz figure lies
within the loop bandwidth. Thus the phase noise
depends on the synthesiser comparator noise floor,
rather than the VCO.
The 10kHz offset figure should depend on the VCO
providing the loop is designed correctly, and is not
underdamped.
There are two ways of achieving a higher phase
comparator sampling frequency:–
A) Reduce the division ratio between the reference
source and the phase comparator
B) use a higher reference source frequency.
Approach B) may be preferred for best performance
since it is possible that the noise floor of the reference
oscillator may degrade the phase comparator
performance if the reference division ratio is very small.
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