SP5768 Datasheet, PDF (5/10 Pages) Zarlink Semiconductor Inc – 3.0 GHz Low Phase Noise Frequency Synthesiser

S₁₁ : _Zo = 50Ω
Normalised to 50Ω
CLOCK
+j1
+j0.5
+j2
SP5768
+j0.2
+j5
0
-j0.2
1
2 _-j5
3
4
Frequency Markers at 500MHz,
-j0.5
-j2
1GHz, 1.5GHz and 2.4GHz
-j1
Figure 3 - RF input impedance
ENABLE
DATA
2²⁷
2²⁶
2²⁵
2²⁴
2²³
2²²
2²¹
2²⁰
2¹⁹
2¹⁸
2¹⁷
2¹⁶
2⁰
P3 P2 P1 _P0
T0
C1
C0
R2 R1
R0
RD MSB
LSB
Frequency data
2^16 to 2^0
R2,R1,R0
RD
P3, P2, P1,P0
C1,C0
T0
: Programmable divider ratio control bits
: Reference divider control bits
: Reference divider mode select
: Port control bits
: Charge pump current select
: Test mode enable
Figure 4 - Data format
C1
C0
Current (in µA)
0
0
230
0
1
1000
1
0
115
1
1
500
Table 1 - Charge pump current
5