SP5654 Datasheet, PDF (8/15 Pages) Zarlink Semiconductor Inc – 2.7GHz 3-WIRE BUS CONTROLLED SYNTHESISER

SP5654
Test Mode
P1
P2
P3
0
0
0
0
1
0
0
1
2
1
0
0
3
1
0
1
4
d
1
0
5
d
1
1
These test modes are invoked by taking the clock input below V_EE
d=don‘t care
Table 2 Test mode options
Test Mode Description
Charge pump down 170mA
Charge pump up 170mA
Charge pump down 50mA
Charge pump up 50mA
F_COMP to P2; F_PD/2 to P3;
Lock output switched to out of lock
condition
Lock output switched to inlock condition
MODE
4
3
2
1
0
COMPATIBILITY
18 Bit Data entry
19 Bit Data entry
TD6380 plus 2 prescaler
TD6382 plus 4 prescaler
None
TD6381
TD6380
TD6382 plus 2 prescaler
None
TD6382
None
TD6381 plus 2 prescaler
Table 3. Programming compatibilities
CLOCK
ENABLE
18–BIT
DATA ENTRY MSB 2¹⁷ 2¹⁶ 2¹⁵ 2¹⁴ 2¹³ 2¹²
P0 P1 P2 P3
2² 2¹ 2⁰ LSB
19–BIT
DATA ENTRY MSB 2¹⁸ 2¹⁷ 2¹⁶ 2¹⁵ 2¹⁴ 2¹³
P0 P1 P2 P3
FREQUENCY DATA
2² 2¹ 2⁰ LSB
t_CE t_ES
FREQUENCY DATA
t_LO
t_Hi
t_EH
CLOCK
3V
1.5V
ENABLE
DATA
3V
1.5V
3V
1.5V
t_SU
t_HD
MSB IS TRANSMITTED
FIRST
t _ES =Enable set up time
t _SU =Data set up time
t _{HD =Data hold time}
t _CE =Clock–to–enable time
t _EH =Enable hold time
t _LO =Clock low period
t _Hi =Clock high period
Fig. 4 Data format and timing
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