SP5654 Datasheet, PDF (6/15 Pages) Zarlink Semiconductor Inc – 2.7GHz 3-WIRE BUS CONTROLLED SYNTHESISER

SP5654
+j1
+j0.5
+j2
+j0.2
+j5
0
0.2
0.5
X
2.6GHz
X
1
2
5
X
–j0.2
X
X
–j5
S₁₁:Z₀ = 50W
NORMALISED TO 50W
–j0.5
–j2 _{FREQUENCY MARKER STEP = 500MHz}
–j1
Fig. 2 Typical input impedance
13
RF
INPUTS
14
5
CLOCK
4
DATA
10
ENABLE
MODE3
SELECT
PRE
AMP
PRESCALER
16
14/15 BIT
FPD
PROGRAMMABLE
DIVIDER
PHASE
COMP
F
REFERENCE
DIVIDER
FCOMP _512/640/1024
/1280/2048
OSC
12
VCC
2
CRYSTAL
DATA
18/19
LATCH
CHARGE
PUMP
DATA
INPUT
INTERFACE
CLOCK
MODE
SELECT
CONTROL
OUTPUT
BUFFER
CP DIS
VA DIS
6 78 9
P3 P2 P1 P0
Fig. 3 Block diagram
LOCK
DETECT
11
LOCK
AMP
1 _CHARGE
PUMP
DRIVE/
VARICAP
OUTPUT
16
15
VEE
4