ZL50110_06 Datasheet, PDF (79/103 Pages) Zarlink Semiconductor Inc – 128, 256 and 1024 Channel CESoP Processors

ZL50110/11/14
Data Sheet
TDM_TXCLK
TDM_TXDATA
TDM_RXCLK
TDM_RXDATA
t_CTP
t_CTH
t_PD
t_CRP
t_CRH
t_S
t_H
t_CTL
t_CRL
Figure 32 - TDM-LIU Structured Transmission/Reception
11.5 PAC Interface Timing
Parameter
TDM_CLKiP High / Low
Pulsewidth
TDM_CLKiS High / Low
Pulsewidth
Symbol
t_CPP
t_CSP
Min.
10
10
Typ.
-
-
Max.
-
-
Table 31 - PAC Timing Specification
Units
ns
ns
Notes
11.6 Packet Interface Timing
Data for the MII/GMII/TBI packet switching is based on Specification IEEE Std. 802.3 - 2000.
11.6.1 MII Transmit Timing
Parameter
Symbol
Min.
100 Mbps
Typ.
Max.
TXCLK period
t_CC
-
40
-
TXCLK high time
t_CHI
14
-
26
TXCLK low time
t_CLO
14
-
26
TXCLK rise time
t_CR
-
-
5
TXCLK fall time
t_CF
-
-
5
TXCLK rise to TXD[3:0] active
t_DV
1
delay (TXCLK rising edge)
-
25
TXCLK to TXEN active delay
t_EV
1
(TXCLK rising edge)
-
25
Table 32 - MII Transmit Timing - 100 Mbps
Units
Notes
ns
ns
ns
ns
ns
ns Load = 25 pF
ns Load = 25 pF
79
Zarlink Semiconductor Inc.