ZL50110_06 Datasheet, PDF (11/103 Pages) Zarlink Semiconductor Inc – 128, 256 and 1024 Channel CESoP Processors

ZL50110/11/14
Data Sheet
1.0 Changes Summary
The following table captures the changes from the February 2006 issue.
Page
86
Item
Table 38, Table 38 - External
Memory Timing
Added Minimum Values
The following table captures the changes from the April 2005 issue.
Change
Page
41, 42
57
Item
Section 3.6 and Section 3.7.2
Section 6.3
Change
Clarified ZL50111 supports 3 MII ports, ZL50110/4 support 2 MII
ports.
Added external pull-up/pull-down resistor recommendations for
SYSTEM_RST, SYSTEM_DEBUG, JTAG_TRST, JTAG_TCK.
Added Section 6.3 SYSTEM_CLK Considerations.
The following table captures the changes from the January 2005 issue.
Page
Item
89
Figure 44
89
Figure 45
Change
Clarified data sheet to indicate ZL5011x supports clock
recovery in both synchronous and asynchronous modes of
operation.
Inverted polarity of CPU_DREQ0 and CPU_DREQ1 to conform
with default MPC8260. Polarity of CPU_DREQ and
CPU_SDACK remains programmable through API.
Inverted polarity of CPU_DREQ0 and CPU_DREQ1 to conform
with default MPC8260. Polarity of CPU_DREQ and
CPU_SDACK remains programmable through API.
The following table captures the changes from the October 2004 issue.
Page
42
Item
Section 3.7.1
Change
Added 5 kohm pulldown recommendation to GPIO signals.
The following table captures the changes from the September 2004 issue.
Page
12, 16, 19
73
98
Item
Fig. 2 and Ball Signal
Assignment Table
DC Electrical Characteristics
Table and Output Levels Table
Section 13.3
Change
Corrected Mx_LINKUP_LED pin assignment.
Changed Electrical Characteristics to differentiate between
3.3 V and 5 V tolerant signals.
New section added; Mx_LINKUP_LED Outputs.
11
Zarlink Semiconductor Inc.