ZL50110_06 Datasheet, PDF (32/103 Pages) Zarlink Semiconductor Inc – 128, 256 and 1024 Channel CESoP Processors

ZL50110/11/14
Data Sheet
Signal
M1_LINKUP_LED
M1_ACTIVE_LED
M1_GIGABIT_LED
M1_REFCLK
M1_RXCLK
M1_RBC0
M1_RBC1
M1_COL
MII Port 1
I/O
Package Balls
Description
O G23 on ZL50110/4
F26 on ZL50111
O AB25
O G25
I D M22
I U M23
I U U26
I U T25
I D R25
LED drive for MAC 1 to indicate port is linked
up.
Logic 0 output = LED on
Logic 1 output = LED off
LED drive for MAC 1 to indicate port is
transmitting or receiving packet data.
Logic 0 output = LED on
Logic 1 output = LED off
LED drive for MAC 1 to indicate operation at
Gbps.
Logic 0 output = LED on
Logic 1 output = LED off
GMII/TBI - Reference Clock input at
125 MHz. Can be used to lock receive
circuitry (RX) to M1_GTXCLK rather than
recovering the RXCLK (or RBC0 and
RBC1). Useful, for example, in the absence
of valid serial data.
NOTE: In MII mode this pin must be driven
with the same clock as M1_RXCLK.
GMII/MII - M1_RXCLK.
Accepts the following frequencies:
25.0 MHz MII 100 Mbps
125.0 MHz GMII 1 Gbps
TBI - M1_RBC0.
Used as a clock when in TBI mode. Accepts
62.5 MHz and is 180°C out of phase with
M1_RBC1. Receive data is clocked at
each rising edge of M1_RBC1 and
M1_RBC0, resulting in 125 MHz sample
rate.
TBI - M1_RBC1
Used as a clock when in TBI mode. Accepts
62.5 MHz, and is 180° out of phase with
M1_RBC0. Receive data is clocked at each
rising edge of M1_RBC1 and M1_RBC0,
resulting in 125 MHz sample rate.
GMII/MII - M1_COL.
Collision Detection. This signal is
independent of M1_TXCLK and
M1_RXCLK, and is asserted when a
collision is detected on an attempted
transmission. It is active high, and only
specified for half-duplex operation.
Table 10 - MII Port 1 Interface Package Ball Definition
32
Zarlink Semiconductor Inc.