ZL50022_06 Datasheet, PDF (75/121 Pages) Zarlink Semiconductor Inc – Enhanced 4 K Digital Switch with Stratum 4E DPLL

ZL50022
Data Sheet
External Read Only Address: 0069_H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R3
R3
R3
R3
R2
R2
R2
R2
R1
R1
R1
R1
R0
R0
R0
R0
FML FMU
FL
FU
FML FMU
FL
FU
FML FMU
FL
FU
FML FMU
FL
FU
Bit
Name
Description
3
R0FML Reference 0 Multi-period Lower Limit Fail Bit
If the device sets this bit to high, the input REF0 fails the multi-period lower limit check.
(See Table 12, “Multi-period Hysteresis Limits” on page 46)
2
R0FMU Reference 0 Multi-period Upper Limit Fail Bit
If the device sets this bit to high, the input REF0 fails the multi-period upper limit
check. (See Table 12, “Multi-period Hysteresis Limits” on page 46)
1
R0FL Reference 0 Single Period Lower Limit Fail Bit
If the device sets this bit to high, the input REF0 fails the single-period lower limit
check. (See Table 11, “Values for Single Period Limits” on page 45)
0
R0FU Reference 0 Single Period Upper Limit Fail Bit
If the device sets this bit to high, the input REF0 fails the single-period upper limit
check. (See Table 11, “Values for Single Period Limits” on page 45)
Table 41 - Reference Failure Status Register (RSR) Bits - Read Only (continued)
External Read/Write Address: 006A_H
Reset Value: 0000_H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R3
R3
R3
R3
R2
R2
R2
R2
R1
R1
R1
R1
R0
R0
R0
R0
MML MMU ML
MU MML MMU ML
MU MML MMU ML
MU MML MMU ML
MU
Bit
Name
Description
15
R3MML Reference 3 Multi-period Lower Limit Mask Bit
When this bit is high, it masks the multi-period lower limit check (or forces pass) for
REF3.
14
R3MMU Reference 3 Multi-period Upper Limit Mask Bit
When this bit is high, it masks the multi-period upper limit check (or forces pass) for
REF3.
13
R3ML Reference 3 Single-period Lower Limit Mask Bit
When this bit is high, it masks the single-period lower limit check (or forces pass) for
REF3.
12
R3MU Reference 3 Single-period Upper Limit Mask Bit
When this bit is high, it masks the single-period upper limit check (or forces pass) for
REF3.
Table 42 - Reference Mask Register (RMR) Bits
75
Zarlink Semiconductor Inc.