ZL50022_06 Datasheet, PDF (44/121 Pages) Zarlink Semiconductor Inc – Enhanced 4 K Digital Switch with Stratum 4E DPLL

ZL50022
Data Sheet
CKo0
CKo1
CKo2
CKo3
CKo4
CKo5
FPo0
FPo1
FPo2
FPo3
FPo5
4.096 MHz
8.192 MHz
16.384 MHz
4.096 MHz, 8.192 MHz, 16.384 MHz or 32.768 MHz
1.544 MHz or 2.048 MHz
19.44 MHz
8 kHz (244 ns wide pulse)
8 kHz (122 ns wide pulse)
8 kHz (61 ns wide pulse)
8 kHz (244 ns, 122 ns, 61 ns or 30 ns wide pulse)
8 kHz (51 ns wide pulse)
Table 10 - Generated Output Frequencies
13.4 Pull-In/Hold-In Range (also called Locking Range)
The widest tolerance required for any of the given input clock frequencies is ±130 ppm for the T1 clock
(1.544 MHz). If the system clock (crystal/oscillator) accuracy is ±30 ppm, it requires a minimum pull-in range of
±160 ppm.Users who do not require the ±30 ppm freerun accuracy of the DPLL can use a ±100 ppm system clock.
Therefore the pull-in range is a minimal ±230 ppm. The pull-in range of this device is ±260 ppm.
14.0 Jitter Performance
14.1 Input Clock Cycle to Cycle Timing Variation Tolerance
The ZL50022 has an exceptional cycle to cycle timing variation tolerance of 20 ns. This allows the ZL50022
to synchronize off a low cost DPLL when it is in either Divided Slave mode or Multiplied Slave mode.
14.2 Input Jitter Acceptance
The input jitter acceptance is specified in standards as the minimum amount of jitter of a certain frequency on the
input clock that the DPLL must accept without making cycle slips or losing lock. The lower the jitter frequency, the
larger the jitter acceptance. For jitter frequencies below a tenth of the cut-off frequency of the DPLL's jitter transfer
function, any input jitter will be followed by the DPLL. The maximum value of jitter tolerance for the DPLL is
±1023UI_p-p.
14.3 Jitter Transfer Function
The corner frequency (-3 dB) of the Stratum 4E DPLL is 15.2 Hz.
15.0 DPLL Specific Functions and Requirements
15.1 Lock Detector
To determine if the DPLL is locked to the input clock, a lock detector monitors the phase value output of the phase
detector, which represents the difference between input reference and output feedback clock. If the phase value is
below a certain threshold for a certain interval, the DPLL is pronounced locked to the input clock. The monitoring is
done in intervals of 4 ms. The lock detector threshold and the interval are programmable by the user through the
Lock Detector Threshold Register (LDTR) and the Lock Detector Interval Register (LDIR) respectively. See
Table 33 on page 67 and Table 34 on page 68 for the bit descriptions of the Lock Detector Threshold Register
(LDTR) and Lock Detector Interval Register (LDIR) respectively. The value of the Lock Detector Threshold Register
44
Zarlink Semiconductor Inc.