SP5610 Datasheet, PDF (7/15 Pages) Zarlink Semiconductor Inc – 1.3GHz BI-DIRECTIONAL I2C BUS CONTROLLED SYNTHESISER

SP5610
ADDRESS
PROGRAMMABLE
DIVIDER
PROGRAMMABLE
DIVIDER
CONTROL DATA
IO PORT CONTROL
DATA
ADDRESS
STATUS BYTE
MSB
LSB
1
1
0
0
0
MA1
MA0
0
0
2¹⁴
2¹³
2¹²
2¹¹
2¹⁰
2⁹
2⁸
2⁷
2⁶
2⁵
2⁴
2³
2²
2¹
2⁰
1
CP
T1
T0
TS2
TS1
TS0
OS
P7
P6
P5
P4
P3
X
X
X
Table 1 Write data format (MSB is transmitted first)
1
1
0
0
0
MA1
MA0
1
POR
FL
I2
I1
I0
A2
A1
A0
Table 2 Read data format (MSB is transmitted first)
A:
MA1, MA0:
CP:
T1:
T0:
TS2, TS1, TS0:
OS:
P7,P6,P5,P4,P3:
POR:
FL:
I2, I1, I0:
A2, A1, A0:
X:
Acknowledge bit
Variable address bits (see Table 4)
Charge pump current select
Test mode enable
Charge pump disable
Operation mode control bits (see Table 5)
Varactor drive Output disable Switch
Control output states
Power On Reset indicator
Phase Lock detect Flag
Digital information from Ports P7, P5 and P4, respectively
5 Level ADC data from P6 (see Table 3)
Don’t care
A
Byte 1
A
Byte 2
A
Byte 3
A
Byte 4
A
Byte 5
A
Byte 1
A
Byte 2
A2
A1
A0
Voltage input to P6
1
0
0
0.6V_CC to 13.2V
0
1
1
0.45V_CC to 0.6V_CC
0
1
0
0.3V_CC to 0.45V_CC
0
0
1
0.15V_CC to 0.3V_CC
0
0
0
0 to 0.15V_CC
Table 3 ADC levels
MA1
0
0
1
1
MA0
Voltage input to P3
0
0 – 0.2V_CC
1
ALWAYS VALID
0
0.3V_CC – 0.7V_CC
1
0.8V_CC – 13.2V
Table 4 Address selection
T1
TS2
TS1
0
X
X
0
X
X
1
0
0
1
0
1
1
1
0
1
1
0
1
1
1
X=don’t care
For further details of test modes see Table 6.
TS0
OPERATION MODE DESCRIPTION
0
Normal operation, test modes disabled, reference divider ratio=1024
1
Normal operation, test modes disabled, reference divider ratio=512
X
Charge pump source (down). Status byte bit FL set to 0
X
Charge pump sink (up). Status byte bit FL set to 1
0
Ports P4,P5,P6,P7 set to state X
1
Port P7=F_PD/2; P4,P5,P6 set to state X
X
Port P7=F_PD; P6=F_COMP; P4, P5 set to state X
Table 5 Operation modes
Fig. 3 Data formats
5