MA838 Datasheet, PDF (7/13 Pages) Zarlink Semiconductor Inc – SINGLE PHASE PULSE WIDTH MODULATION WAVEFORM GENERATOR

MA838
Initialisation Register Function
The 24-bit initialisation register contains parameters which,
under normal operation, will be defined during the power-up
sequence. These parameters are particular to the drive circuitry
used, and therefore changing these parameters during a PWM
cycle is not recommended. Information in this register should
only be modified while RST is active (i.e. low) so that the PWM
outputs are inhibited (low) during the updating process.
The parameters set in the initialisation register are as
follows:
Carrier frequency
Low carrier frequencies reduce switching losses whereas
high carrier frequencies increase waveform resolution and can
allow ultrasonic operation.
Power Frequency Range
This sets the maximum power frequency that can be carried
within the PWM output waveforms. This would normally be set
to a value to prevent the motor system being operated outside
its design parameters.
Pulse delay time ('underlap')
For each phase of the PWM cycle there are two control
signals, one for the top switch connected to the positive
inverter DC supply and one for the bottom switch connected to
the negative inverter DC supply. In theory, the states of these
two switches are always complementary. However, due to the
finite and non-equal turn-on and turn- off times of power
devices, it is desirable when changing the state of the output
pair, to provide a short delay time during which both outputs are
off in order to avoid a short circuit through the switching
elements.
Pulse deletion time
A pure PWM sequence produces pulses which can vary in
width between 0% and 100% of the duty cycle. Therefore, in
theory, pulse widths can become infinitesimally narrow. In
practice this causes problems in the power switches due to
storage effects and therefore a minimum pulse width time is
required. All pulses shorter than the minimum specified are
deleted.
Counter reset
This facility allows the internal power frequency counter of
the MA838 to be set to zero, disabling the normal frequency
control and giving a 50% output duty cycle.
CFS word
101 100 011 010 001 000
Value of n
32 16 8 4 2 1
Table 4 Values of clock division ratio n
The carrier frequency, f_CARR, is then given by:
f_CARR
=
k
512 x
n
where k = clock frequency and n = 1, 2, 4, 8, 16 or 32 (as set
by FRS)
Power frequency range selection
The power frequency range selected here defines the maximum
limit of the power frequency. The operating power frequency is
controlled by the 12-bit Power Frequency Select (PFS) word in the
control register but may not exceed the value set here.
The power frequency range is a function of the carrier
waveform frequency (f_CARR) and a multiplication factor m,
determined by the 3-bit FRS word. The value of m is determined
as shown in Table 5.
FRS word 110 101 100 011 010 001 000
Value of m 64 32 16 8 4 2 1
Table 5 Values of carrier frequency multiplicaion factor m
The power frequency range, f_RANGE, is then given by:
f_RANGE
= ^fCARR
384
x
m
where f_CARR = carrier frequency and m = 1, 2, 4, 8, 16, 32 or
64 (as set by FRS).
Initialisation Register Programming
The initialisation register data is loaded in 8-bit segments into
the three 8-bit temporary registers R0-R2. When all the initialisation
data has been loaded into these registers it is transferred into the
24-bit initialisation register by writing to the dummy register R4.
Fig. 7 Temporary register R2
Pulse delay time
The pulse delay time affects all six PWM outputs by delaying
the rising edges of each of the outputs by an equal amount.
The pulse delay time is a function of the carrier waveform
frequency and pdy, defined by the 6-bit pulse delay time select
word (PDY). The value of pdy is selected as shown in Table 6.
PDY word
Value of pdy
111111 111110 ...etc...
1
2
...etc...
Table 6 Values of pdy
000000
64
Fig. 6 Temporary register R1
Carrier frequency selection
The carrier frequency is a function of the externally applied
clock frequency and a division ratio n, determined by the 3-bit
CFS word set during initialisation. The values of n are selected
as shown in Table 4.
The pulse delay time, t_pdy, is then given by:
t_pdy
=
pdy
f_CARR x 512
where pdy = 1- 64 (as set by PDY) and f_CARR = carrier
frequency.
6