MA838 Datasheet, PDF (6/13 Pages) Zarlink Semiconductor Inc – SINGLE PHASE PULSE WIDTH MODULATION WAVEFORM GENERATOR

MA838
Fig. 4 Intel bus timing definitions
Fig. 5 Motorola bus timing definitions
Parameter
Symbol Min. Units
ALE high period
t₁
70
ns
Delay time, ALE to WR
t₂
40
ns
WR low period
t₃
200
ns
Delay time, WR high to ALE high t₄
40
ns
CS setup time
t₈
20
ns
CS hold time
t₉
0
ns
Address setup time
t₁₀
30
ns
Address hold time
t₁₅
30
ns
Data setup time
Data hold time
t₁₁
100
ns
t₁₂
25
ns
Table 1 Intel bus timings at V_DD = 5V, T_AMB = 25°C
CONTROLLING THE MA838
The MA838 is controlled by loading data into two 24-bit
registers via the microprocessor interface. These registers
are the initialisation register and the control register.
The initialisation register would normally be loaded prior to
the PWM outputs being activated and sets up the basic
operating parameters associated with the load and inverter.
This data would not normally be updated during PWM
operation.
The control register is used to control the PWM outputs
(and hence the load) during operation e.g., stop/start, speed
etc. and would normally be loaded and changed only after the
initialisation register has been loaded.
As the MOTEL bus interface is restricted to an 8-bit wide
format, data to be loaded into either of the 24-bit register is
first written to three 8-bit temporary registers R0, R1 and R2
before being transferred to the desired 24-bit register. The
data is accepted (and acted upon) only when transferred to
one of the 24-bit registers.
Parameter
Symbol Min. Units
AS high period
t₁
90
ns
Delay time, as low to DS high
t₂
40
ns
DS high period
t₃
210
ns
Delay time, DS low to AS high
t₄
40
ns
DS low period
t₅
200
ns
DS high to R/W low setup time
t₆
10
ns
R/W hold time
t₇
10
ns
CS setup time
t₈
20
ns
CS hold time
t₉
0
ns
Address setup time
t₁₀
30
ns
Address hold time
t₁₅
30
ns
Write data setup time
t₁₁
110
ns
Write data hold time
t₁₂
30
ns
Table 2 Motorola bus timings at V_DD = 5V, T_AMB = 25°C
Transfer of data from the temporary registers to either the
initialisation register or the control register is achieved by a
write instruction to a dummy register. Writing to dummy register R3
results in data transfer from R0, R1 and R2 to the control register,
while writing to dummy register R4 transfers data from R0, R1
and R2 to the initialisation register. It does not matter what data
is written to the dummy registers R3 and R4 as they are not real
registers. It is merely the write instruction to either of these
registers which is acted upon in order to load the initialisation and
control registers.
AD₂ AD₁ AD₀ Register
Comment
000
R0 Temporary register R0
001
R1 Temporary register R1
010
R2 Temporary register R2
011
R3 Transfers control data
100
R4 Transfers initialisation data
Table 3 MA838 register addressing
5