MA838 Datasheet, PDF (5/13 Pages) Zarlink Semiconductor Inc – SINGLE PHASE PULSE WIDTH MODULATION WAVEFORM GENERATOR

MA838
PWM
SWITCHING
INSTANTS
+1
0
-1
+1
0
SAMPLING
POINTS
TRIANGLE WAVE AT
CARRIER FREQUENCY
POWER
WAVEFORM AS
READ FROM
INTERNAL
ROM
RESULTING
PWM
WAVEFORM
-1
Fig.3 Asynchronous PWM generation with uniform or 'double-edged' regular sampling as used on the MA838
FUNCTIONAL DESCRIPTION
An asynchronous method of PWM generation is used with
uniform or ‘double-edged’ regular sampling of the waveform
stored in the internal ROM as illustrated in Fig. 3. Two standard
waveshape options exist so that the device can be adapted to
particular applications (see PRODUCT DESIGNATION section
for details). In addition, any symmetrical waveshape may be
integrated on-chip, to order.
The triangle carrier wave frequency is selectable up to
24kHz (assuming the maximum clock frequency of 12.5MHz is
used), enabling ultrasonic operation for noise critical
applications. With 12.5MHz clock, power frequency ranges of
up to 4kHz are possible, with the actual output frequency
resolved to 12-bit accuracy within the chosen range in order to
give precise motor speed control and smooth frequency
changing.
PWM output pulses can be ‘tailored’ to the inverter
characteristics by defining the minimum allowable pulse width
(deletes all shorter pulses from the ‘pure’ PWM pulse train) and
the pulse delay (underlap) time without the need for external
circuitry. This gives cost advantages in both component savings
and in allowing the same PWM circuitry to be used for control
of a number of different systems simply by changing the
microprocessor software.
Power frequency amplitude control is also provided with an
overmodulation option to assist in rapid motor braking.
Alternatively, braking may be implemented by setting the
frequency to 0Hz. This is termed ‘DC injection braking’, in
which the rotation of the motor is opposed by allowing DC to
flow in the windings.
A trip input allows the PWM outputs to be shut down
immediately, overriding the microprocessor control in the event
of an emergency.
Other possible MA838 applications are as a waveform
generator as part of a switched-mode power supply (SMPS)
or an uninterruptible power supply (UPS). In such applications
the high carrier frequency allows a very small transformer to
be used.
MICROPROCESSOR INTERFACE
The MA838 interfaces to the controlling microprocessor by
means of a multiplexed bus of the MOTEL format. This interface
bus has the ability to adapt itself automatically to the format and
timing of both MOTorola and IntEL interface buses (hence
MOTEL). Internally, the detection circuitry latches the status of
the DS/RD line when AS/ALE goes high. If the result is high
then the Intel mode is used; if the result is low then the Motorola
mode is used. This procedure is carried out each time that AS/
ALE goes high. In practice this mode selection is transparent
to the user. For bus connection and timing information refer to
the description relevant to the microprocessor/controller being
used.
Industry standard microprocessors such as the 8085, 8088,
etc. and microcontrollers such as the 8051, 8052 and 6805 are
all compatible with the interface on the MA838. This interface
consists of 8 data lines, AD₀ - AD₇ (write-only in this instance),
which are multiplexed to carry both the address and data
information, 3 bus control lines, labelled WR,RD and ALE in
Intel mode and R/W, DS and AS in Motorola mode, and a Chip
Select input CS, which allows the MA838 to share the same
bus as other microprocessor peripherals. It should be noted
that all bus timings are derived from the microprocessor and
are independent of the MA838 clock input.
Intel Mode (Fig. 4 and Table 1)
The address is latched by the falling edge of ALE. Data is
written from the bus into the MA838 on the rising edge of WR.
RD is not used in this mode because the registers in the MA838
are write only. However, this pin must be connected to RD (or
tied high) to enable the MA838 to select the correct interface
format.
Motorola Mode (Fig. 5 and Table 2)
The address is latched on the falling edge of the AS line.
Data is written from the bus into the MA838 (only when R/W is
low) on the falling edge of DS (providing CS is low).
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