MT9074_05 Datasheet, PDF (63/151 Pages) Zarlink Semiconductor Inc – T1/E1/J1 Single Chip Transceiver

MT9074
Data Sheet
Bit
Name
Functional Description
3
LUA
Loop Up Activate. Setting this bit forces transmission of a framed or
unframed (depending on the state of Transmit Alarm Control bit 0)
repeating pattern of 00001.
2
LDA
Loop Down Activate. Setting this bit forces transmission of a framed or
unframed (depending on the state of Transmit Alarm Control bit 0)
repeating pattern of 001.
1
D4SECY
D4 Secondary Alarm. Set this bit for trunks employing the secondary
Yellow Alarm. The Fs bit in the 12th frame will not be used for counting
errored framing bits. If a one is received in the Fs bit position of the 12th
frame a Secondary Yellow Alarm Detect bit will be set.
0
SO
Overhead Sbits Override. If set, this bit forces the overhead bits to be
inserted as an overlay on any of the following alarm conditions: i) transmit
all ones, ii) loop up code insertion, iii) loop down code insertion.
Table 22 - Transmit Alarm Control Word (T1)
(Page 1, Address 11H)
Bit
Name
Functional Description
7
EDL
Enable Data Link. Setting this bit multiplexes the serial stream clocked in
on pin TxDL into the FDL bit position (ESF mode) or the Fs position (D4
mode).
6
BIOMEn
Bit Oriented Messaging Enable. Setting this bit enables transmission of
bit - oriented messages on the ESF facility data link. The actual message
transmit at any one time is contained in the BIOMTx register (page 1,
address 13H). The receive bit - oriented message register is always active,
although the interrupt associated with it may be masked.
5
HDLC0
HDLC0 Enable. Setting this bit selects the internal HDLC controller for
transmission of data link information in the FDL Sbits of an ESF frame. The
HDLC receiver is always active, although interrupts associated with it may
be masked.
4
HDLC1
HDLC1 Enable. Setting this bit selects the internal HDLC controller for
transmission on DS1 channel 24. The HDLC receiver is always active,
although interrupts associated with it may be masked.
3
TxSYNC
Transmit Synchronization. Setting this bit causes the transmit multiframe
boundary to be internally synchronized to the incoming Sbits on DSTi
channel 31 bit 0.
2
TRSP
Transparent Mode. Setting this bit causes unframed data to be transmit
from DSTi channels 0 to 23 and channel 31 bit 0 to be transmit
transparently onto the DS1 line. Unframed data received from the DS1 line
is piped out on DSTo channels 0 to 23 and channel 31 bit 0.
Table 23 - Data Link Control Word (T1)
(Page 1, Address 12H)
63
Zarlink Semiconductor Inc.