MT9074_05 Datasheet, PDF (129/151 Pages) Zarlink Semiconductor Inc – T1/E1/J1 Single Chip Transceiver

MT9074
Data Sheet
Bit
Name
Functional Description
7
INTSEL
Interrupt Selection. When high, this bit will cause bit 2 of the Interrupt
Register to reflect a TX FIFO underrun (TXunder). When low, this interrupt
will reflect a frame abort (FA).
6
CYCLE
Cycle. When high, this bit will cause the transmit byte count to cycle through
the value loaded into the Transmit Byte Count Register.
5
TxCRCI
Transmit CRC Inhibited. When high, this bit will inhibit transmission of the
CRC. That is, the transmitter will not insert the computed CRC onto the bit
stream after seeing the EOP tag byte. This is used in V.120 terminal
adaptation for synchronous protocol sensitive UI frames.
4
SEVEN
Seven Bit Address Recognition. When high, this bit will enable seven bits
of address recognition in the first address byte. The received address byte
must have bit 0 equal to 1 which indicates a single address byte is being
received.
3
RSV
Reserved, must be zero for normal operation.
2
RSV
Reserved, must be zero for normal operation.
1
RxFRST
RX FIFO Reset. When high, the RX FIFO will be reset. This causes the
receiver to be disabled until the next reception of a flag. The status register
will identify the FIFO as being empty. However, the actual bit values in the
RX FIFO will not be reset.
0
TxFRST
TX FIFO Reset. When high, the TX FIFO will be reset. The Status Register
will identify the FIFO as being empty. This bit will be reset when data is
written to the TX FIFO. However, the actual bit values of data in the TX
FIFO will not be reset. It is cleared by the next write to the TX FIFO.
Table 146 - HDLC Control Register 2
(Page B & C, Address 15H)
Bit
Name
Functional Description
7-0
GaIM
This register is used with the Interrupt Register to mask out the interrupts
RxEOPIM
TxEOPIM
RxFEIM
TxFLIM
FA:TxUNDERIM
RxFFIM
that are not required by the microprocessor. Interrupts that are masked out
will not drive the pin IRQ low; however, they will set the appropriate bit in the
Interrupt Register. An interrupt is disabled when the microprocessor writes a
0 to a bit in this register.
This register is cleared on power reset.
RxOVFIM
Table 147 - HDLC Interrupt Mask Register
(Page B & C, Address 16H)
129
Zarlink Semiconductor Inc.