MT9074_05 Datasheet, PDF (1/151 Pages) Zarlink Semiconductor Inc – T1/E1/J1 Single Chip Transceiver

MT9074
T1/E1/J1 Single Chip Transceiver
Data Sheet
Features
• Combined E1 (PCM30) and T1 (D4/ESF) framer,
Line Interface Unit (LIU) and link controller with
optional digital framer only mode
• In T1 mode the LIU can recover signals
attenuated by up to 30 dB (5000 ft. of 24 AWG
cable)
• In E1 mode the LIU can recover signals
attenuated by up to 30 dB (1900 m. of 0.65 mm
cable)
• Two HDLCs: FDL and channel 24 in T1 mode,
timeslot 0 (Sa bits) and timeslot 16 in E1 mode
• Two-frame elastic buffer in Rx & Tx (T1)
directions
• Programmable transmit delay through transmit
slip buffer
• Low jitter DPLL for clock generation
• Enhanced alarms, performance monitoring and
error insertion functions
• Intel or Motorola non-multiplexed parallel
microprocessor interface
• ST-BUS 2.048 Mbit/s backplane bus for both data
and signaling
• Japan Telecom J1 Framing and Yellow Alarm
TxDL TxDLCLK TxMF
August 2005
Ordering Information
MT9074AL
100 Pin MQFP
MT9074AP
MT9074APR
MT9074AL1
MT9074AP1
MT9074APR1
68 Pin PLCC
68 Pin PLCC
100 Pin MQFP*
68 Pin PLCC*
68 Pin PLCC*
*Pb Free Matte Tin
-40°C to +85°C
Trays
Tubes
Tape & Reel
Trays
Tubes
Tape & Reel
• Hardware data link access
• JTAG Boundary Scan
Applications
• E1/T1 add/drop multiplexers and channel banks
• CO and PBX equipment interfaces
• Primary Rate ISDN nodes
• Digital Cross-connect Systems (DCS)
* MT9074A was revised after its market introduction. Software can
confirm that the installed chip is the most recent revision of MT9074A
as follows:
1. In T1 mode, the LSB (Least Significant Bit) of the
Synchronization Status Word - bit 0, Page 3 Address 10H is set
high.
2. Batch codes 61755.0 or higher, and/or date code beginning with
00, 01, 02, etc.
TxAO TxB TxA
DSTi
CSTi
Tdi
Tdo
Tms
Tclk
Trst
IRQ
D7~D0
AC4
AC0
R/W/WR
CS
DS/RD
DSTo
CSTo
ST-BUS
Interface
Transmit Framing, Error,
Test Signal Generation and Slip Buffer
Line
Driver
ST Loop
PL Loop
Data Link,
HDLC0
HDLC1
National
Bit Buffer
CAS
Buffer
Jitter Attenuator
& Clock Control
DG Loop
ST-BUS
Interface
Receive Framing, Performance Monitoring,
Alarm Detection, 2 Frame Slip Buffer
TTIP
TRING
S/FR
BS/LS
OSC1
OSC2
RTIP
RRING
RxDLCLK RxDL RxMF
LOS
RxFP
E1.5o F0b C4b
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2002-2005, Zarlink Semiconductor Inc. All Rights Reserved.