MA3864 Datasheet, PDF (6/11 Pages) Zarlink Semiconductor Inc – RADIATION HARD 8192 x 8 BIT MASK-PROGRAMMABLE ROM

TIMING DIAGRAMS
MA3864
Address
Q
1. E and G = V_IL
TAVQV
TAXQX
Figure 9: Address Controlled Read Cycle
Address
_
E*
TAVAX
TAVQV
TELQX
TELQV
TELEH
TEHQZ
Q
1. G = V_IL
2. Address valid prior to or coincident with E transition low
3. *See footnote to Figure 5
Figure 10: Chip Select Controlled Read Cycle
5