ZL50011 Datasheet, PDF (59/83 Pages) Zarlink Semiconductor Inc – Flexible 512 Channel DX with on-chip DPLL

ZL50011
Data Sheet
External Read/Write Address: 111_H, 113_H,
Reset Value: 0000_H
115_H, 117_H,
119_H,
11B_H, 11D_H,
11F_H,
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SIDR8
0
0
0
0
0
0
STIN8
STIN8
STIN8
STIN8
STIN8
STIN8
STIN8
STIN8B STIN8B STIN8B
CD6
CD5
CD4
CD3
CD2
CD1
CD0
BD2
BD1
BD0
SIDR9
0
0
0
0
0
0
STIN9
STIN9
STIN9
STIN9
STIN9
STIN9
STIN9
STIN9B STIN9B STIN9B
CD6
CD5
CD4
CD3
CD2
CD1
CD0
BD2
BD1
BD0
SIDR10
0
0
0
0
0
0
STIN10
STIN10
STIN10
STIN10
STIN10
STIN10
STIN10
STIN10
STIN10
STIN10
CD6
CD5
CD4
CD3
CD2
CD1
CD0
BD2
BD1
BD0
SIDR11
0
0
0
0
0
0
STIN11
STIN11
STIN11
STIN11
STIN11
STIN11
STIN11
STIN11
STIN11
STIN11
CD6
CD5
CD4
CD3
CD2
CD1
CD0
BD2
BD1
BD0
SIDR12
0
0
0
0
0
0
STIN12
STIN12
STIN12
STIN12
STIN12
STIN12
STIN12
STIN12
STIN12
STIN12
CD6
CD5
CD4
CD3
CD2
CD1
CD0
BD2
BD1
BD0
SIDR13
0
0
0
0
0
0
STIN13
STIN13
STIN13
STIN13
STIN13
STIN13
STIN13
STIN13
STIN13
STIN13
CD6
CD5
CD4
CD3
CD2
CD1
CD0
BD2
BD1
BD0
SIDR14
0
0
0
0
0
0
STIN14
STIN14
STIN14
STIN14
STIN14
STIN14
STIN14
STIN14
STIN14
STIN14
CD6
CD5
CD4
CD3
CD2
CD1
CD0
BD2
BD1
BD0
SIDR15
0
0
0
0
0
0
STIN15
STIN15
STIN15
STIN15
STIN15
STIN15
STIN15
STIN15
STIN15
STIN15
CD6
CD5
CD4
CD3
CD2
CD1
CD0
BD2
BD1
BD0
Bit
Name
Description
15 - 10
9-3
Unused
STIN#CD6 - 0
Reserved. In normal functional mode, these bits MUST be set to zero.
Input Stream# Channel Delay Bits:
The binary value of these bits refers to the number of channels that the input
stream will be delayed. This value should not exceed the maximum channel
number of the stream. Zero means no delay.
2-0
STIN#BD2 - 0
Input Stream# Bit Delay Bits:
The binary value of these bits refers to the number of bits that the input stream
will be delayed. This maximum value is 7. Zero means no delay.
Note: # denotes input stream from 8 to 15
Table 27 - Stream Input Delay Register 8 to 15 (SIDR8 to SIDR15)
59
Zarlink Semiconductor Inc.