ZL50011 Datasheet, PDF (30/83 Pages) Zarlink Semiconductor Inc – Flexible 512 Channel DX with on-chip DPLL

ZL50011
Data Sheet
Memory block programming procedure:
(Assumption: The MBPE and MBPS bits are both low at the start of the procedure)
• Program Bit 1 to 3 (BPD0 to BPD2) in the IMS (Internal Mode Selection) register.
• Set the Memory Block Programming Enable (MBPE) bit in the Control Register to high to enable the block
programming mode.
• Set the Memory Block Programming Start (MBPS) bit to high in the IMS Register to start the block
programming. The BPD0 to BPD2 bits will be loaded into Bit 0 to 2 of the connection memory. The other bit
positions of the connection memory will be loaded with zeros. The memory content after block programming
is shown in Table 8.
• It takes 50µs for the connection memory to be loaded with the bit pattern defined by the BPD0 to BPD2 bits.
• After loading the bit pattern to the entire connection memory, the device will reset the MBPS bit to low,
indicating that the process has finished.
• Upon completion of the block programming, set the MBPE bit from high to low to disable the block
programming mode.
Note: Once the block programming is started, it can be terminated at any time prior to completion by setting the
MBPS bit or the MBPE bit to low. If the MBPE bit is used to terminate the block programming before completion,
users have to set the MBPS bit from high to low before enabling other device operation.
11 10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0 BPD2 BPD1 BPD0
Table 8 - Connection Memory in Block Programming Mode
2.6 Bit Error Rate (BER) Test
The ZL50011 has one on-chip BER transmitter and one BER receiver. The transmitter can transmit onto a single
STo output stream only. The transmitter provides a BER sequence (2¹⁵-1 Pseudo Random Code) which can start
from any channel in the frame and lasts from one channel up to one frame time (125 µs). The transmitter output
channel(s) are specified by programming the connection memory location(s) corresponding to the channel(s) of the
selected output stream: Bit 0 to 2 of the connection memory location(s) should be programmed to the BER test
mode (see Table 34 on page 65).
Multiple connection memory locations can be programmed for BER test such that the BER patterns can be
transmitted for several output channels which are consecutive. If the transmitting output channels are not
consecutive, the BER receiver will not compare the bit patterns correctly.
The number of output channels which the BER transmitter occupies also has to be the same as the number of
channels defined in the BER Length Register. The BER Length Register defines how many BER channels to be
monitored by the BER receiver.
Registers used for setting up the BER test are as follows:
• Control Register (CR) - The CBER bit is used to clear the bit error counter and the BER Count Register
(BCR). The SBER bit is used to start or stop the BER transmitter and BER receiver.
• BER Start Receiving Register (BSRR) - Defines the input stream and channel from where the BER
sequence will start to be compared.
• BER Length Register (BLR) - Defines how many channels the sequence will last.
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Zarlink Semiconductor Inc.