ZL50011 Datasheet, PDF (39/83 Pages) Zarlink Semiconductor Inc – Flexible 512 Channel DX with on-chip DPLL

ZL50011
Data Sheet
Figure 29 - Detailed DPLL Jitter Transfer Function Diagram (Wander Transfer Diagram)
2.11.5 Locking Range
The locking range is the input frequency range over which the DPLL must be able to pull into synchronization and to
maintain the synchronization. The locking range is defined by the Loop Filter circuit and is equal to +/- 298 ppm.
Note that the locking range is related to the oscillator frequency. If the oscillator frequency is -100 ppm, the whole
locking range also shifts by -100 ppm downwards to become -398 ppm to +198 ppm.
2.11.6 Phase Slope
The phase slope, or phase alignment speed, is the rate at which a given signal changes phase with respect to an
ideal signal. The given signal is typically the output signal. The ideal signal is of constant frequency and is nominally
equal to the value of the final output signal or final input signal. Many telecom standards state that the phase slope
may not exceed a certain value, usually 81 ns/1.327 ms (61 ppm). This can be achieved by limiting the phase
detector output to 61 ppm or less.
For the DPLL, the Phase Slope Limiter circuit limits the maximum phase slope to 56 ppm or 7 ns/125 µs. The phase
slope limit meets Telcordia GR-1244-CORE requirements.
2.11.7 Phase Lock Time
The Phase Lock Time is the time it takes a synchronizer to phase lock to the input signal. Phase lock occurs when
the input and the output signals are not changing in phase with respect to each other (not including jitter).
Lock time is very difficult to determine because it is affected by many factors which include:
i) initial input to output phase difference
ii) initial input to output frequency difference
iii) PLL loop filter
iv) PLL limiter
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Zarlink Semiconductor Inc.