ZL50011_06 Datasheet, PDF (47/83 Pages) Zarlink Semiconductor Inc – Flexible 512 Channel DX with on-chip DPLL

7.0 Detail Register Description
ZL50011
Data Sheet
External Read/Write Address: 000_H
Reset Value: 0000_H
15
14 13 12
11
10
9
8
7
6
5
4
3
2
1
0
FBD SLV FBD CKIN CKIN CKIN CKFP CKFP CKFP CBER SBER MBPE OSB MS2 MS1 MS0
MODE
EN
2
1
0
2
1
0
Bit
15
14
13
12 - 10
Name
FBD-
MODE
SLV
FBDEN
CKIN2-0
Description
Frame Boundary Determination Mode Select.
When either the FBDEN or FBDMODE bit is set low, the frame boundary discriminator
(FBD) is disabled.
When both the FBDEN and FBDMODE bits are set HIGH, the frame discriminator (FBD)
is enabled. The device will have 20 ns of input clcok jitter tolerance (on CKi and FPi)
when the FBD is enabled.
By default, the FBDEN and FBDMODE bits are Low. Both the FBDEN and FBDMODE
bits should be set HIGH during normal operation.
DPLL Bypass Mode Enable.
When this bit is zero, the DPLL is in Master or Freerun mode. When this bit is high, the
DPLL is in Bypass mode.
Frame Boundary Determinator Enable.
When either the FBDEN or FBDMODE bit is set low, the frame boundary discriminator
(FBD) is disabled.
When both the FBDEN and FBDMODE bits are set HIGH, the frame discriminator (FBD)
is enabled. The device will have 20ns of input clcok jitter tolerance (on CKi and FPi)
when the FBD is enabled.
By default, the FBDEN and FBDMODE bits are Low. Both the FBDEN and FBDMODE
bits should be set HIGH during normal operation.
Input ST Bus Clock (CKi) and Frame Pulse (FPi) Selection.
CKIN2 - 0
000
001
010
011 - 111
FPi Low Cycle
CKi
61 ns
122 ns
244 ns
16.384 MHz
8.192 MHz
4.096 MHz
Reserved
9
CKFP2 Output ST Bus clock CKo2 and frame pulse FPo2 Selection.
When this bit is low, CKo2 is 32.768 MHz clock and FPo2 is 30 ns wide frame pulse
When this bit is high, CKo2 is 16.384 MHz clock and FPo2 is 61 ns wide frame pulse
8
CKFP1 Output ST Bus clock CKo1 and frame pulse FPo1 Selection.
When this bit is low, CKo1 is 16.384 MHz clock and FPo1 is 61 ns wide frame pulse
When this bit is high, CKo1 is 8.192 MHz clock and FPo1 is 122 ns wide frame pulse
7
CKFP0 Output ST Bus clock CKo0 and frame pulse FPo0 Selection.
When this bit is low, CKo0 is 4.096 MHz clock and FPo0 is 244 ns wide frame pulse
When this bit is high, CKo0 is 8.192 MHz clock and FPo0 is 122 ns wide frame pulse
Table 16 - Control Register (CR) Bits
47
Zarlink Semiconductor Inc.