SP5026 Datasheet, PDF (4/11 Pages) Zarlink Semiconductor Inc – 1.0GHz 3-Wire Bus Controlled Synthesizer

Data Sheet
SP5026
The FC_COMP is obtained by dividing the output of an on-chip crystal controlled oscillator. The crystal frequency used
is generally 4MHz, which gives an F_COMP of 3.90625kHz/7.815kHz and, when multiplied back up to the synthesized
LO, gives a minimum step size of 31.25kHz/62.5kHz, respectively.
The programmable divider is preceded by an input RF preamplifier and high speed, low radiation prescaler. The
preamplifier is arranged to be self oscillating, so giving excellent input sensitivity. The input sensitivity and
impedance are shown in Figure 5 and Figure 7 respectively.
The SP5026 contains an improved lock detect circuit which generates a flag when the loop has attained lock. “Out
of Lock” is indicated by high impedance state.
The SP5026 contains 4 general purpose open collector outputs, ports P1-P4, which are capable of sinking at least
10mA. These outputs are set by the remaining four bits within the normal data word.
Pin Compatibility
The SP5026 may by used in SP5510 applications which require 3-wire bus as opposed to 1²C bus data format. In
SP5510 applications where the reference crystal is connected to pin 3, a small modification is required to ground
the crystal as shown in Figure 4.
Appropriate connections to the mode select input (pin 3) must also be made.
In mode 1 (pin 3 “HIGH”) the SP5026 is programming and step size compatible with the Toshiba TD6380, and in
mode 2 (pin 3 “LOW”) it is compatible with the TD6381.
Zarlink Semiconductor Inc.
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