SP5026 Datasheet, PDF (3/11 Pages) Zarlink Semiconductor Inc – 1.0GHz 3-Wire Bus Controlled Synthesizer

SP5026
Data Sheet
The comparator has a charge pump output with an amplifier stage around which feedback may be applied. Only
one external transistor is required for varicap line driving.
Figure 2 - Pin Connections - Top View
Functional Description
The SP5026 contains all the elements necessary, with the exception of reference crystal, loop filter and external
high voltage transistor to control a voltage controlled local oscillator, so forming a PLL frequency synthesized
source.
The system is controlled by a microprocessor via a standard data, clock enable three-wire bus. The data load
normally consists of a single word, which contains the frequency and port information and is only transferred to the
internal data shift register during an enable high period. The clock input is disabled during enable low periods.
New data words are only accepted by the internal data buffers from the shift register on a negative transition of the
enable, so giving improved fine tune facility for digital AFC etc.
The data sequence and timing follows the format shown in Figure 3.
The frequency is set by loading the programmable divider with the required 14/15 bit divisor word. The output of the
divider, F_PD, is fed to the phase comparator where it is compared in phase and frequency domain to the internal
generated comparison frequency, F_COMP.
2
Zarlink Semiconductor Inc.