MT90401 Datasheet, PDF (25/38 Pages) Zarlink Semiconductor Inc – SONET/SDH System Synchronizer

MT90401
Data Sheet
5.5 Output Phase Adjustment
Two control registers are available to program the output phase offset of the generated clocks. All 16.384 MHz
derived outputs clocks, F16o, F80, F0o, C16o, C8o, C4o and C2o can be collectively shifted up to 125
microseconds with a step size of 60 nS with respect to the input reference by programming the Set Delay Word 1
and Set Delay Word 2 registers.
Control and Status Registers
Address
(A₆A₅A₄A₃A₂A₁A₀)
Register
00H (Table 6)
Control Register 1
Read/
Write
Function
Read/ RSEL, FS2, FS1, MS2, MS1, SONET/SDH
Write FLOCK, TCLR
01H (Table 7)
Status Register 1
Read PRIOOR, SECOOR, LOCK, HOLDOVER,
Only RSV, FLim, RSV, RSV
02H
Reserved
Read
Only
03H
Reserved
Read
Only
04H (Table 8)
Control Register 2
Read/ E3/DS3/OC3, E3/DS3, RSV=0, RSV=0,
Write RSV=0, RSV=0, RSV=0, RSV=0.
05H
Reserved
Read Set all bits to zero.
/Write
06H (Table 9)
Set Delay Word 2
Read/ RSV=0, RSV=0, RSV=0, RSV=0, OffEn,
Write C16OCNT10,C16OCNT9, C16OCNT8
07H (Table 10)
Set Delay Word 1
Read/ C16OCNT7-0
Write
08H
Reserved
Read/ Set all bits to zero.
Write
09H
Reserved
Read
Only
0AH
Reserved
Read
Only
0BH
Reserved
Read
Only
0CH
Reserved
Read
Only
0DH
Reserved
Read
Only
Table 5 - Register Map
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