MT90401 Datasheet, PDF (17/38 Pages) Zarlink Semiconductor Inc – SONET/SDH System Synchronizer

MT90401
Data Sheet
2.5 Transitions from Freerun Mode or Holdover Mode to Normal Mode
Telcordia GR-253-CORE requires SONET Internal Clocks to settle within 100 s after transitioning from Freerun
Mode or Holdover Mode to Normal Mode. During such a transition, the wander filtering requirements for a SONET
Internal Clock are relaxed to make a 100 s settling time possible.
To meet the GR-253-CORE 100 s settling time requirement at power-up and during a transition from Freerun Mode
to Normal Mode the MT90401 should be placed in its SDH Mode until lock is achieved. When the PLL indicates
lock the MT90401 should be placed in SONET Mode.
During a transition from Holdover Mode to Normal Mode, GR-253-CORE requires a SONET Internal Clock to limit
the frequency slope to less than 2.9 ppm per second. To meet the 100 s settling time during such a transition it is
necessary to keep the MT90401 in SONET Mode and Fast Lock Mode until lock is achieved. When the PLL
indicates lock the MT90401 can be taken out of its Fast Lock Mode.
A transition from Holdover Mode to Normal Mode can result in a large initial frequency offset, for example 4.6 ppm,
between the clock’s reference and its output. The 2.9 ppm per second frequency slope limit required by
GR-253-CORE places a lower limit on the time it takes for a SONET Internal Clock to acquire a new frequency.
While the clock is acquiring the new frequency a phase error will accumulate which could cause the clock’s settling
time to be longer than 100 s. GR-1244-CORE and GR-253-CORE allow a clock to ignore some of the phase error
accumulated during the transition from Holdover Mode to Normal Mode.
During a transition from Holdover Mode to Normal Mode, if the MT90401 has not achieved lock within 16 seconds,
it is recommended that the PLL be put briefly into its Holdover Mode and then returned to Normal Mode by toggling
the MS1 pin or the MS1 control bit. Toggling the PLL into and out of Holdover will clear any accumulated phase
error and reduce the settling time.
3.0 MT90401 Measures of Performance
The following are some synchronizer performance indicators and their corresponding definitions.
3.1 Jitter Generation
Jitter generation is the amount of jitter produced by a PLL and is measured at its output. It is measured by applying
a reference signal with no jitter to the input of the device, and measuring its output jitter. Jitter generation may also
be measured when the device is in a non-synchronizing mode, such as free running or holdover, by measuring the
output jitter of the device. Jitter generation is usually measured with various band-limiting filters depending on the
applicable standards.
3.2 Jitter Tolerance
Jitter tolerance is a measure of the ability of a PLL to operate properly (i.e., remain in lock and or regain lock in the
presence of large jitter magnitudes at various jitter frequencies) when jitter is applied to its reference. The applied
jitter magnitude and jitter frequency depends on the applicable standards (see Figures 7, 8 and 9).
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Zarlink Semiconductor Inc.