MT90401 Datasheet, PDF (16/38 Pages) Zarlink Semiconductor Inc – SONET/SDH System Synchronizer

MT90401
Data Sheet
2.1 Normal Mode
Normal Mode is typically used when a slave clock source, synchronized to the network is required.
In Normal Mode, the MT90401 provides timing and frame synchronization signals, which are synchronized to one
of two reference inputs (PRI or SEC). The input reference signal may have a nominal frequency of 8 kHz,
1.544 MHz, 2.048 MHz or 19.44 MHz.
The selection of input references is control dependent as shown in state table 4. The reference frequencies are
selected by the frequency control pins/bits FS2 and FS1 as shown in Table 1.
2.2 Holdover Mode
Holdover Mode is typically used when network synchronization is temporarily disrupted.
In Holdover Mode, the MT90401 provides timing and synchronization signals, which are not locked to an external
reference signal, but are based on storage techniques. The storage value is determined while the device is in
Normal Mode and locked to an external reference signal
When in Normal Mode, and locked to the input reference signal, a numerical value corresponding to the MT90401
output reference frequency is stored alternately in two memory locations every 30 ms. When the device is switched
into Holdover Mode, the value in memory from between 30 ms and 60 ms is used to set the output frequency of the
device.
The frequency accuracy of Holdover Mode is ±0.02 ppm, which translates to a worst case 14 frame (125 us) slips
in 24 hours. This is better than the Telcordia GR-1244-CORE Stratum 3 requirement of ±0.37 ppm (255 frame slips
per 24 hours).
Two factors affect the accuracy of Holdover Mode. One is drift on the Master Clock and the other is jitter on the
reference signal. The drift on the Master Clock oscillator propagates unattenuated and causes the same drift on the
output clocks. This drift can only be reduced by selecting more stable Master Clock oscillator. For example, a
±4.6 ppm temperature compensated clock oscillator may have a temperature coefficient of 0.03 ppm per degree C.
The 10 degC change while in Holdover Mode, will result in an additional offset in frequency accuracy equal to
0.3ppm which is much greater than the internal holdover accuracy of the MT90401 (0.02 ppm).
The other factor affecting accuracy is large jitter on the reference input prior (30 ms to 60 ms) to the mode switch.
For instance, jitter of 7.5 UI at 700 Hz may reduce the Holdover Mode accuracy from 0.02 ppm to 0.10 ppm.
2.3 Freerun Mode
Freerun Mode is typically used when a master clock source is required, or immediately following system power-up
before network synchronization is achieved. In Freerun Mode, the MT90401 provides timing and synchronization
signals which are based on the master clock frequency (C20i) only, and are not synchronized to the reference
signals (PRI and SEC).
The accuracy of the output clock is equal to the accuracy of the master clock (C20i). So if a ±20 ppm output clock is
required, the master clock must also be ±20 ppm. See Applications - Master Clock section.
2.4 Fast Lock Mode
Fast Lock Mode is a submode of Normal Mode, it is used to allow the MT90401 to lock to a reference eight times
more quickly than normal. Fast Lock Mode necessarily compromises the wander generation characteristics of the
MT90401. When the MT90401 is in Fast Lock Mode and SONET Mode at the same time, the PLL frequency slope
is limited to less than 1.9 ppm per second.
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Zarlink Semiconductor Inc.