YSS915 Datasheet, PDF (8/32 Pages) YAMAHA CORPORATION – Karaoke Processor 2 for Video disc player

YSS915
4. Digital audio interface
SDSY, BCI,DI, L/R,DO,BCO
-1) Digital audio signal is inputted through BCI, SDSY and DI pins using the following format.
BCI
SDSY
DI(16bit )
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DI(18bit )
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DI(20bit )
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DI(24bit )
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Lch
Rc h
-2) Digital audio signal is outputted through BCO, L/R, and DO pins using the following format.
BCO
L/R
DO(16bit )
DO(18bit )
DO(20bit )
DO(24bit )
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Lch
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Rc h
-3) The digital audio interface is made compatible with the following format with OPR register ($00) and DAR register
($04).
Format
Format1
Format2
Format3
Format4
BCI
-
32-96fs
64fs
48fs
-
BCO
64fs
64fs
BCI
64fs
OPR
[5]
1
0
0
0
0
0
Format1
Use this format when digital audio input is not used.
DAR
[3:2]
*
0
1
2
3
*
MDR
[3]
0
0
Available
mode
N,E
N,E
0
E
1
E
N=KP2 standard mode
E=KP2V extended mode
Format2
Use this format when digital audio input is used.
BCI is able to accept any frequency between including 96fs from 32fs, while BCO outputs only 64 fs.
BCI, SDSY and DI signals must be synchronized with XI clock.
Format3
Use this format when digital audio input is used.
BCI input signal is passed to the BCO output, being inverted.
SDSY input signal is passed to the L/R output, being delayed by 2.5 clocks of BCI.
BCI, SDSY and DI signals must be synchronized with XI clock.
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