YGV627 Datasheet, PDF (8/16 Pages) YAMAHA CORPORATION – AVDP3E - Advanced Video Display processor 3 Enhanced

YGV627
q VR64 ( I: PULL UP )
High level is inputted when the capacity of SDRAM that is used as a video memory controlled by YGV627 is 16M
bits, or low level is inputted when the capacity is 64M bits. This signal determines the function of signal outputted
from BA1, BA0, and VA11–VA0 pins. Connect with the SDRAM as specified below.
Since this pin is for selection of a mode, always fix it to either level.
5 VR64 = “H” (when connected with 16M bit SDRAM)
YGV627 pins
SDRAM pins
CS RAS CAS WE BA1 BA0 VA11 VA10 VA9 VA8 VA7−0
CS RAS CAS WE
A11 A10 A9 A8 A7−0
5 VR64 = “L” (when connected with 64M bit SDRAM)
YGV627 pins
SDRAM pins
CS RAS CAS WE BA1
CS RAS CAS WE A13
BA0 VA11 VA10 VA9
A12 A11 A10 A9
VA8
A8
VA7−0
A7−0
< Display monitor interface>
q R, G, B ( O: Analog output )
These pins output linear RGB signal. When a termination resistor of 37.5 Ω is connected, voltage amplitude with
resolution of 8 bits (256 levels) is outputted. These pins can directly drive a monitor whose impedance is 75 Ω as
shown below.
R(G,B)
RL=75Ω
RL=75Ω
q IREF ( I: Analog input )
Reference current for RGB DAC is inputted to this pin. The reference current of – 9.38 mA provides amplitude of
0.7 Vp-p (typical value). When supplying the reference current, use a current sink circuit as shown below.
For the following circuit, adjust the values of R1 and R2 so that the pin potential of IREF (V_IREF) become
approximately 1.37 V.
IREF
R1
R2
(Current Sink Circuit)
R1
q CSYNC ( O )
This pin outputs a composite sync signal to external monitor. In interlace mode, it outputs equivalent pulse.
q VSYNC ( O )
This pin outputs vertical sync signal to external monitor.
q HSYNC ( O )
This pin outputs horizontal sync signal to external monitor.
q _BLANK ( O )
This pin outputs a signal that indicates non-display period (blank period). Therefore, it can be used as a signal that
indicates valid display period for LCD panel.
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