YGV627 Datasheet, PDF (10/16 Pages) YAMAHA CORPORATION – AVDP3E - Advanced Video Display processor 3 Enhanced

YGV627
q HSIN ( I: PULL UP )
This signal resets the horizontal timing of CRT controller block of YGV627.
The horizontal timing is set to the horizontal sync starting position at the moment this signal falls from high level to
low level, and at the same time, the phase of dot clock is reset.
When the built-in PLL is operated in the external sync mode, the input signal and output of HSYNC pin are locked.
If this signal is inputted during the display period, the display data of the next line is not guaranteed.
This pin can be kept open if this function is not used.
The function of this pin is the same as that of HRESET pin of YGV617B.
< Clocks>
q SYCKIN ( I ), SYCKOUT ( O )
Crystal is connected to these pins to generate reference clock that is used in the system.
The built-in PLL produces SDRAM clock based on this clock. When supplying system clock and dot clock using the
same clock through SYSEL pin (when low level is inputted to SYSEL), input the common clock through DTCKIN
pin. At this time, input low level or high level signal into SYCKIN pin. SYCKOUT pin can be kept open.
When inputting externally generated clock, input it into SYCKIN pin.
SYCKIN and SYCKOUT pins are the same as VCKIN and VCKOUT pins of YGV617B.
SYCKIN
SYCKOUT
q SPLLVSSR, SPLLRREF, SPLLFILT ( Analog )
These pins are used to connect external resistors and capacitors for the built-in PLL that produces SDRAM clock.
SPLLFILT
3.3 kΩ
220 pF
SPLLRREF
3.9 kΩ
SPLLVSSR
Notes:
1. Arrange the components so that the parasitic capacitance among SPLLFILT, SPLLRREF and SPLLVSSR is
minimized and the signals do not cross each other.
2. PLL may not lock if there is a time difference between the rising moment of AVDD (for PLL) and the rising
moment of VDD (for Digital Logic).
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