YGV627 Datasheet, PDF (5/16 Pages) YAMAHA CORPORATION – AVDP3E - Advanced Video Display processor 3 Enhanced

YGV627
s PIN FUNCTIONS
<CPU interface>
q D15_−0 ( I/O: PULL UP )
This is a data bus for connecting with external processor. D15−D8 are not used when the CPU bus with 8 bit type
(when low level is inputted to LWD). At this time, keep the D15−D8 open. These pins are provided with pull-up
resistors respectively.
q A22−1 ( I )
This is an address bus to be connected with external general purpose microcomputer. In the indirect access mode
(high level inputted to DMAP pin), input to A22−A4 pins are ignored when accessing CSREG space.
In the direct access mode (low level inputted to DMAP pin), input to A22−A8 pins are ignored when accessing
CSREG space.
YGV627 can be used as a YGV617B compatible device when A22 and A21 pins are fixed to low level. Unused pins
must be set to low level or high level.
q _CSREG ( I )
It is a chip select signal input to register space (I/O). When this chip select signal is active, the read / write pulses
inputted are made valid so that the registers in the YGV627 are accessed.
The function of this pin is the same as that of CSIO pin of YGV617B.
q CSMEM ( I )
This is a chip select signal input pin for video memory port. The read / write pulse inputted while this signal is active
can be used to directly access the video memory controlled by YGV627.
It is possible not to use CSMEM because the video memory can also be accessed from registers. In such case, it is
necessary to input high level to CSMEM pin.
q A0 / WR1, WR0 ( I )
When chip select input is active, these pins control write access to YGV627.
D15−D8 are controlled by A0 / WR1, and D7−D0 by WR0.
When the CPU is 8 bit type, A0 / WR1 functions as CPU address bit 0.
q RD ( I )
When chip select input is active, RD controls read access from YGV627.
D15−D0 are in Output State in the period while both this signal and chip select signals are active.
q READY ( O: PULL UP, 3-state output )
This is data ready signal output to CPU. The READY signal is made low when the internal state of YGV627 is
accessible. READY is a 3-state output. When CSREG or CSMEM (hereafter called CS signals) is not active, it is
high impedance state, and when CS signals is active and RD or WR1, WR0 is not active, high level is outputted
from READY.
Some CPU must use WAIT signal instead of this signal.
A22-A1
CS
A0/WR1, WR0
D15-D0
¯R¯E¯A¯D¯Y¯
Hi-Z
VALID
VALID
Hi-Z
READY signal at write access
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