DS073 Datasheet, PDF (8/15 Pages) Xilinx, Inc – Cascadable for storing longer or multiple bitstreams

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Table 6: Truth Table for XC17V00 Control Inputs
Control Inputs
RESET⁽¹⁾
CE
Inactive
Low
Internal Address
If address < TC⁽²⁾: increment
If address > TC⁽²⁾: don’t change
Active
Low
Held reset
Inactive
High
Not changing
Active
High
Held reset
Notes:
1. The XC17V00 RESET input has programmable polarity
2. TC = terminal count, highest address value.
XC17V00 Series Configuration PROMs
DATA
Active
High-Z
High-Z
High-Z
High-Z
Outputs
CEO
High
Low
High
High
High
I_CC
Active
Reduced
Active
Standby
Standby
DS073 (v1.12) November 13, 2008
www.xilinx.com
Product Specification
8