DS073 Datasheet, PDF (2/15 Pages) Xilinx, Inc – Cascadable for storing longer or multiple bitstreams

R
X-Ref Target - Figure 1
VCC VPP _GND
XC17V00 Series Configuration PROMs
RESET/
OE
CE
or
OE/
RESET
CLK
CEO
Address Counter _TC
EPROM
Cell
Matrix
Output
OE
DATA
X-Ref Target - Figure 2
DS073_01_072600
Figure 1: Simplified Block Diagram for XC17V04, XC17V02⁽¹⁾, and XC17V01
(does not show programming circuit)
VCC VPP _GND
RESET/
OE
CE
or
OE/
RESET
CEO
CLK
BUSY
Address Counter _TC
EPROM
Cell
Matrix
Output 8
OE
7
7
D0 Data
(Serial or Parallel Mode)
D[1:7]
(SelectMAP Interface)
Figure 2: Simplified Block Diagram for XC17V16 and XC17V08⁽¹⁾
(does not show programming circuit)
DS073_02_031506
DS073 (v1.12) November 13, 2008
www.xilinx.com
Product Specification
2