DS073 Datasheet, PDF (12/15 Pages) Xilinx, Inc – Cascadable for storing longer or multiple bitstreams

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XC17V00 Series Configuration PROMs
AC Characteristics over Operating Condition for XC17V16 and XC17V08
X-Ref Target - Figure 5
CE
RESET/OE⁽¹⁾
CLK
DATA
BUSY⁽²⁾
TSCE
TOE
TCE
TLC
THC
TCAC
TSBUSY
TCEH
TSCE
TCYC
THOE
TOH
TDF
THBUSY
TOH
THCE
Note:
1 The XC17V00 RESET/OE input polarity is programmable. The RESET/OE input is shown in the timing diagram with active-high RESET polarity.
Timing specifications are identical for both polarity settings.
2. If BUSY is inactive (Low) during a rising CLK edge, then new DATA appears at time TCAC after the rising CLK edge. If BUSY is active (High)
during a rising CLK edge, then there is no corresponding change to DATA.
DS073_05_031606
Symbol
Description
Min
Max
T_OE
T_CE
T_CAC
T_DF
T_OH
T_CYC
T_LC
T_HC
T_SCE
T_HCE
T_HOE
T_SBUSY
T_HBUSY
T_CEH
OE to data delay
CE to data delay
CLK to data delay⁽²⁾
CE or OE to data float delay^(3,4)
Data hold from CE, OE, or CLK⁽⁴⁾
Clock periods
CLK Low time⁽⁴⁾
CLK High time⁽⁴⁾
CE setup time to CLK (to guarantee proper counting)
CE hold time to CLK (to guarantee proper counting)
OE hold time (guarantees counters are reset)
BUSY setup time
BUSY hold time
CE High time (guarantees counters are reset)
–
15
–
20
–
20
–
35
0
–
50
–
25
–
25
–
25
–
0
–
25
–
5
–
5
–
20
–
Notes:
1. AC test load = 50 pF.
2. When BUSY = 0.
3. Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady state active levels.
4. Guaranteed by design, not tested.
5. All AC parameters are measured with V_IL = 0.0V and V_IH = 3.0V.
6. If T_CEH High, 2 μs, T_CE = 2 μs.
7. If T_HOE High, 2 μs, T_OE = 2 μs.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS073 (v1.12) November 13, 2008
www.xilinx.com
Product Specification
12