XC5VFX130T-2FF1738I Datasheet, PDF (5/13 Pages) Xilinx, Inc – Virtex-5 Family Overview

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Virtex-5 Family Overview
RocketIO GTP Transceivers (LXT/SXT only)
• Full-duplex serial transceiver capable of 100 Mb/s to
3.75 Gb/s baud rates
• 8B/10B, user-defined FPGA logic, or no encoding
options
• Channel bonding support
• CRC generation and checking
• Programmable pre-emphasis or pre-equalization for
the transmitter
• Programmable termination and voltage swing
• Programmable equalization for the receiver
• Receiver signal detect and loss of signal indicator
• User dynamic reconfiguration using secondary
configuration bus
• Out of Band (OOB) support for Serial ATA (SATA)
• Electrical idle, beaconing, receiver detection, and PCI
Express and SATA spread-spectrum clocking support
• Less than 100 mW typical power consumption
• Built-in PRBS Generators and Checkers
RocketIO GTX Transceivers (TXT/FXT only)
• Full-duplex serial transceiver capable of 150 Mb/s to
6.5 Gb/s baud rates
• 8B/10B encoding and programmable gearbox to
support 64B/66B and 64B/67B encoding, user-defined
FPGA logic, or no encoding options
• Channel bonding support
• CRC generation and checking
• Programmable pre-emphasis or pre-equalization for
the transmitter
• Programmable termination and voltage swing
• Programmable continuous time equalization for the
receiver
• Programmable decision feedback equalization for the
receiver
• Receiver signal detect and loss of signal indicator
• User dynamic reconfiguration using secondary
configuration bus
• OOB support (SATA)
• Electrical idle, beaconing, receiver detection, and
PCI Express spread-spectrum clocking support
• Low-power operation at all line rates
PowerPC 440 RISC Cores (FXT only)
• Embedded PowerPC 440 (PPC440) cores
− Up to 550 MHz operation
− Greater than 1000 DMIPS per core
− Seven-stage pipeline
− Multiple instructions per cycle
− Out-of-order execution
− 32 Kbyte, 64-way set associative level 1 instruction
cache
− 32 Kbyte, 64-way set associative level 1 data cache
− Book E compliant
• Integrated crossbar for enhanced system performance
− 128-bit Processor Local Buses (PLBs)
− Integrated scatter/gather DMA controllers
− Dedicated interface for connection to DDR2 memory
controller
− Auto-synchronization for non-integer PLB-to-CPU clock
ratios
• Auxiliary Processor Unit (APU) Interface and Controller
− Direct connection from PPC440 embedded block to
FPGA fabric-based coprocessors
− 128-bit wide pipelined APU Load/Store
− Support of autonomous instructions: no pipeline stalls
− Programmable decode for custom instructions
DS100 (v5.0) February 6, 2009
www.xilinx.com
Product Specification
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