XC5VFX130T-2FF1738I Datasheet, PDF (10/13 Pages) Xilinx, Inc – Virtex-5 Family Overview

Virtex-5 Family Overview
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Virtex-5 TXT and FXT Platform Features
This section describes blocks only available in TXT and FXT devices.
RocketIO GTX Serial Transceivers
One or Two PowerPC 440 Processor Cores
(TXT/FXT)
(FXT only)
8 - 48 channels RocketIO serial transceivers capable of
running 150 Mb/s to 6.5 Gb/s
• Full Clock and Data Recovery
• 8/16/32-bit or 10/20/40-bit datapath support
• Optional 8B/10B encoding, gearbox for programmable
64B/66B or 64B/67B encoding, or FPGA-based
encode/decode
• Integrated FIFO/Elastic Buffer
• Channel bonding and clock correction support
• Dual embedded 32-bit CRC generation/checking
• Integrated programmable character detection
• Programmable de-emphasis (AKA transmitter
equalization)
• Programmable transmitter output swings
• Programmable receiver equalization
• Programmable receiver termination
• Embedded support for:
− Serial ATA: Out of Band (OOB) signalling
− PCI Express: Beaconing, electrical idle, and receiver
detection
• Built-in PRBS generator/checker
Virtex-5 FPGA RocketIO GTX transceivers are further
discussed in the Virtex-5 FPGA RocketIO GTX Transceiver
User Guide.
• Superscalar RISC architecture
• 32-bit Book E compliant
• 7-Stage execution pipeline
• Multiple instructions per cycle
• Out-of-order execution
• Integrated 32 KB Level 1 Instruction Cache and 32KB
Level 1 Data Cache (64-way set associative)
• CoreConnect™ Bus Architecture
• Cross-bar connection for optimized processor
bandwidth
• PLB Synchronization Logic (Enables non-integer CPU-
to-PLB clock ratios)
• Auxiliary Processor Unit (APU) interface with an
integrated APU controller
− Optimized FPGA-based Coprocessor connection
- Automatic decode of PowerPC floating-point
instructions
− Allows custom instructions
− Extremely efficient microcontroller-style interfacing
The PowerPC 440 processors are further discussed in the
Embedded Processor Block in Virtex-5 FPGAs Reference
Guide.
Intellectual Property Cores
Xilinx offers IP cores for commonly used complex functions
including DSP, bus interfaces, processors, and processor
peripherals. Using Xilinx LogiCORE™ products and cores from
third party AllianceCORE participants, customers can shorten
development time, reduce design risk, and obtain superior
performance for their designs. Additionally, the CORE Generator™
system allows customers to implement IP cores into Virtex-5
FPGAs with predictable and repeatable performance. It offers a
simple user interface to generate parameter-based cores
optimized for our FPGAs.
The System Generator for DSP tool allows system architects to
quickly model and implement DSP functions using handcrafted IP
and features an interface to third-party system level DSP design
tools. System Generator for DSP implements many of the high-
performance DSP cores supporting Virtex-5 FPGAs including the
Xilinx Forward Error Correction Solution with Interleaver/
De-interleaver, Reed-Solomon encoder/decoders, and Viterbi
decoders. These are ideal for creating highly-flexible,
concatenated codecs to support the communications market.
Using Virtex-5 FPGA RocketIO transceivers, industry leading
connectivity and networking IP cores include leading-edge PCI
Express, Serial RapidIO, Fibre Channel, and 10 Gb Ethernet
cores can be implemented. The Xilinx SPI-4.2 IP core utilizes the
Virtex-5 FPGA ChipSync technology to implement dynamic phase
alignment for high-performance source-synchronous operation.
Xilinx also provides PCI cores for advanced system-synchronous
operation.
The MicroBlaze™ 32-bit processor core provides the industry's
fastest soft processing solution for building complex systems for
the networking, telecommunication, data communication,
embedded, and consumer markets. The MicroBlaze processor
features a RISC architecture with Harvard-style separate 32-bit
instruction and data buses running at full speed to execute
programs and access data from both on-chip and external
memory. A standard set of peripherals are also CoreConnect™
enabled to offer MicroBlaze designers compatibility and reuse.
All IP cores for Virtex-5 FPGAs are found on the Xilinx IP Center
Internet portal presenting the latest intellectual property cores and
reference designs using Smart Search for faster access.
Virtex-5 FPGA LogiCORE Endpoint Block Plus Wrapper
for PCI Express
This is the recommended wrapper to configure the integrated
Endpoint block for PCI Express delivered through the CORE
Generator system. It provides many ease-of-use features and
optimal configuration for Endpoint application simplifying the
design process and reducing the time-to-market. Access to the
core, including bitstream generation capability can be obtained
through registration at no extra charge.
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DS100 (v5.0) February 6, 2009
Product Specification