XC1700E Datasheet, PDF (5/12 Pages) Xilinx, Inc – XC1700E and XC1700L Series

R
V_CC
XC1700E and XC1700L Series Configuration PROMs
D_OUT
FPGA
MODES*
OPTIONAL
Daisy-chained
FPGAs with
Different
configurations
OPTIONAL
Slave FPGAs
with Identical
Configurations
V_CC
RESET
RESET
D_IN
CCLK
DONE
INIT
3.3V
4.7K
V_CC V_PP
DATA
CLK ^PROM
CE
CEO
OE/RESET
* For mode pin connections,
refer to the appropriate FPGA data sheet.
(Low Resets the Address Pointer)
CCLK
(Output)
DATA
CLK
CE
Cascaded
Serial
Memory
OE/RESET
D_IN
D_OUT
(Output)
DS027_02_060100
Figure 2: Master Serial Mode. The one-time-programmable PROM supports automatic loading of configuration programs.
Multiple devices can be cascaded to support additional FPGAs. An early DONE inhibits the PROM data output one CCLK
cycle before the FPGA I/Os become active.
DS027 (v3.1) July 5, 2000
www.xilinx.com
5
Product Specification
1-800-255-7778