XC1700E Datasheet, PDF (2/12 Pages) Xilinx, Inc – XC1700E and XC1700L Series

XC1700E and XC1700L Series Configuration PROMs
Pin Description
DATA
Data output is in a high-impedance state when either CE or
OE are inactive. During programming, the DATA pin is I/O.
Note that OE can be programmed to be either active High or
active Low.
CLK
Each rising edge on the CLK input increments the internal
address counter, if both CE and OE are active.
RESET/OE
When High, this input holds the address counter reset and
puts the DATA output in a high-impedance state. The polar-
ity of this input pin is programmable as either RESET/OE or
OE/RESET. To avoid confusion, this document describes
the pin as RESET/OE, although the opposite polarity is pos-
sible on all devices. When RESET is active, the address
counter is held at "0", and puts the DATA output in a
high-impedance state. The polarity of this input is program-
mable. The default is active High RESET, but the preferred
option is active Low RESET, because it can be driven by the
FPGAs INIT pin.
The polarity of this pin is controlled in the programmer inter-
face. This input pin is easily inverted using the Xilinx
HW-130 Programmer. Third-party programmers have differ-
ent methods to invert this pin.
CE
When High, this pin disables the internal address counter,
puts the DATA output in a high-impedance state, and forces
the device into low-I_CC standby mode.
CEO
Chip Enable output, to be connected to the CE input of the
next PROM in the daisy chain. This output is Low when the
CE and OE inputs are both active AND the internal address
counter has been incremented beyond its Terminal Count
(TC) value. In other words: when the PROM has been read,
CEO will follow CE as long as OE is active. When OE goes
inactive, CEO stays High until the PROM is reset. Note that
OE can be programmed to be either active High or active
Low.
R
V_PP
Programming voltage. No overshoot above the specified
max voltage is permitted on this pin. For normal read oper-
ation, this pin must be connected to V_CC. Failure to do so
may lead to unpredictable, temperature-dependent opera-
tion and severe problems in circuit debugging. Do not leave
V_PP floating!
V_CC and GND
Positive supply and ground pins.
PROM Pinouts
Pin Name
8-pin
PDIP
SOIC
VOIC
20-pin
SOIC
20-pin
PLCC
44-pin
VQFP
44-pin
PLCC
DATA
1
1
2
40
2
CLK
2
3
4
43
5
RESET/OE 3
8
6
13
19
(OE/RESET)
CE
4
10
8
15
21
GND
5
11
10 18, 41 24, 3
CEO
6
13
14
21
27
V_PP
7
18
17
35
41
V_CC
8
20
20
38
44
Capacity
Devices
XC1704L
XC1702L
XC1701/L
XC17512L
XC1736E
XC1765E/EL
XC17128E/EL
XC17256E/EL
Configuration Bits
4,194,304
2,097,152
1,048,576
524,288
36,288
65,536
131,072
262,144
2
www.xilinx.com
DS027 (v3.1) July 5, 2000
1-800-255-7778
Product Specification