DS589 Datasheet, PDF (5/6 Pages) Xilinx, Inc – Virtex-5 FPGA CRC Wizard v1.3

Virtex-5 FPGA CRC Wizard v1.3
Table 3: Virtex-5 Verilog Implementation Resource Utilization
Design Configuration
CRC Width
32
CRC with variable REM support
64
CRC with variable REM support + Transpose CRC
32
Data + Complement CRC Data
64
Resource Used
LUTs
FFs
265
406
489
674
329
406
634
674
Verification
The CRC Wizard was verified using a simulation test bench with a frame-based traffic generator and
checker to verify the integrity of the data transmitted with that received. The designs generated
through CRC Wizard were tested on hardware for functionality, performance, and reliability using the
Xilinx ML523 RocketIO™ characterization platform.
References
1. SP006: LocalLink Interface Specification
2. UG189: Virtex-5 FPGA CRC Wizard v1.3 User Guide
3. UG196: Virtex-5 FPGA RocketIO GTP Transceiver User Guide
4. DS100: Virtex-5 Family Overview
DS589 March 24, 2008
www.xilinx.com
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Product Specification