DS608 Datasheet, PDF (4/5 Pages) Xilinx, Inc – LogiCORE IP System Monitor

LogiCORE IP System Monitor Wizard v2.1
User Attributes
The System Monitor functionality is configured through the control registers (See the Register File
Interface sections in the Virtex-5 and Virtex-6 FPGA System Monitor user guides: [Ref 1] and [Ref 2]).
Table 2 lists the attributes associated with these control registers. These control registers can be
initialized when the SYSMON primitive is instantiated in the HDL using the attributes listed in Table 2.
The control registers can also be initialized through the DRP at run time. The System Monitor Wizard
simplifies the initialization of these control registers in the HDL instantiation. The Wizard will generate
the correct bit patterns based on user functionality selected through the Wizard GUI.
Table 2: System Monitor Attributes
Attribute
Name
Control
Reg
Address
Description
INIT_40
INIT_41
INIT_42
Configuration
register 0
Configuration
register 1
Configuration
register 2
40h
System Monitor configuration registers. For detailed
41h information, see the Virtex-5 and Virtex-6 FPGA
System Monitor user guides ([Ref 1] and [Ref 2])
42h
INIT_48 to INIT_4F
Sequence
registers
48h to 4Fh
Sequence registers used to program the Channel
Sequencer function in the System Monitor. For
detailed information, see the Virtex-5 and Virtex-6
FPGA System Monitor user guides ([Ref 1] and
[Ref 2]).
INIT_50 to INIT_57
Alarm Limits
registers
50h to 57h
Alarm threshold registers for the System Monitor
alarm function. For detailed information, see the
Virtex-5 and Virtex-6 FPGA System Monitor user
guides ([Ref 1] and [Ref 2]).
SIM_MONITOR_FILE Simulation Analog
Entry File
-
This is the text file that contains the analog input
stimulus. This is used for simulation.
SIM_DEVICE
Device family
-
This is used to identify the device family. This is used
for simulation.
Support
Xilinx provides technical support for this LogiCORE product when used as described in the product
documentation. Xilinx cannot guarantee timing, functionality, or support of product if implemented in
devices that are not defined in the documentation, if customized beyond that allowed in the product
documentation, or if changes are made to any section of the design labeled DO NOT MODIFY.
Ordering Information
The System Monitor™ Wizard LogiCORE IP core is provided free of charge under the terms of the
Xilinx End User License Agreement. The core can be generated by the Xilinx ISE CORE Generator
software, which is a standard component of the Xilinx ISE Design Suite. This version of the core can be
generated using the ISE CORE Generator system v12.4. For more information, please visit the
Architecture Wizards web page.
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DS608 December 14, 2010
Product Specification