DS608 Datasheet, PDF (3/5 Pages) Xilinx, Inc – LogiCORE IP System Monitor

LogiCORE IP System Monitor Wizard v2.1
Table 1: System Monitor I/O Signals (Cont’d)
Port
Direction
Description
VAUXP15[15:0]
VAUXN15[15:0]
Inputs
16 auxiliary analog-input pairs. In addition to the dedicated
differential analog-input, the System Monitor uses 16
differential digital-input pairs as low-bandwidth differential
analog inputs. These inputs are configured as analog during
FPGA configuration.
USER_TEMP_ALARM_OUT
Output
System Monitor temperature-sensor alarm output.
VCCINT_ALARM_OUT
VCCAUX_ALARM_OUT
OT_OUT
Output
Output
Output
System Monitor V_CCINT-sensor alarm output.
System Monitor V_CCAUX-sensor alarm output.
Over-Temperature alarm output.
CHANNEL_OUT[4:0]
Outputs
Channel selection outputs. The ADC input MUX channel
selection for the current ADC conversion is placed on these
outputs at the end of an ADC conversion.
EOC_OUT
Output
End of Conversion signal. This signal transitions to an active-
High at the end of an ADC conversion when the measurement
result is written to the status registers. For detailed information,
see the System Monitor Timing section in the Virtex-5 and
Virtex-6 FPGA System Monitor user guides ([Ref 1] and
[Ref 2].)
EOS_OUT
Output
End of Sequence. This signal transitions to an active-High when
the measurement data from the last channel in the Channel
Sequencer is written to the status registers. For detailed
information, see the System Monitor Timing section in the
Virtex-5 and Virtex-6 FPGA System Monitor user guides
([Ref 1] and [Ref 2]).
BUSY_OUT
Output
ADC busy signal. This signal transitions High during an ADC
conversion. This signal transitions High for an extended period
during calibration.
JTAGLOCKED_OUT
Output
Used to indicated that DRP port has been locked by the JTAG
interface.
JTAGMODIFIED_OUT
Output
Used to indicate that a JTAG write to the DRP has occurred.
JTAGBUSY_OUT
Output
Used to indicate that a JTAG DRP transaction is in progress.
DS608 December 14, 2010
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Product Specification