DS484 Datasheet, PDF (4/5 Pages) Xilinx, Inc – The Split Operation has the following features:

Utility Bus Split (v1.00a)
Design Implementation
Design Tools
The Utility Bus Split design is handwritten.
Xilinx XST is the synthesis tool used for synthesizing the Utility Bus Split.
Target Technology
The target technology is an FPGA listed in Supported Device Family field of the LogiCORE IP Facts
Table.
Device Utilization and Performance Benchmarks
This core does not contain any logic. There are no performance benchmarks available.
Specification Exceptions
Not applicable
Reference Documents
None
Support
Xilinx provides technical support for this LogiCORE product when used as described in the product
documentation. Xilinx cannot guarantee timing, functionality, or support of product if implemented in
devices that are not defined in the documentation, if customized beyond that allowed in the product
documentation, or if changes are made to any section of the design labeled DO NOT MODIFY.
Revision History
Date
03/28/03
12/19/03
7/15/04
8/17/04
9/20/04
04/24/09
12/2/09
Version
1.0
1.1
1.2
1.3
1.4
1.5
1.6
Description of Revisions
Revision History added to document.
Added LogiCORE IP Facts table. Reformatted to current Xilinx template.
Minor corrections and updates.
Updated for EDK 6.3. Updated trademarks and supported family device listing.
Corrected C_LEFT_POS description in parameter table. Updated to new data sheet
template
Replaced references to supported device families and tool name(s) with hyperlinks
to PDF files. Updated trademark information.
Listed supported devices families in LogiCORE Table; added Spartan-6 and Virtex-
6 support, converted to new DS template.
4
www.xilinx.com
DS484 December 2, 2009
Product Specification