DS484 Datasheet, PDF (3/5 Pages) Xilinx, Inc – The Split Operation has the following features:

Utility Bus Split (v1.00a)
Parameter-Port Dependencies
Table 3: Port and Parameter Dependencies
Name
Affects
Depends
Design Parameters
C_SIZE_IN
Sig
0 to C_SIZE_IN-1
C_SIZE_IN
Out2
C_SPLIT to C_SIZE_IN-1
C_LEFT_POS Out1
C_LEFT_POS to C_SPLIT-1
C_SPLIT
Out1
C_LEFT_POS to C_SPLIT-1
C_SPLIT
Out2
C_SPLIT to C_SIZE_IN-1
Port Signals
Sig
C_SIZE_IN
Out1
C_LEFT_POS
Out1
C_SPLIT
Out2
C_SPLIT
Out2
C_SIZE_IN
1. Assuming reverse big-endian bit ordering.
Relationship Description
Scale width of input bus
Least ⁽¹⁾ significant bit of Out2 bus
Most ⁽¹⁾ significant bit of Out1 bus
Least ⁽¹⁾ significant bit of Out1 bus
Most ⁽¹⁾ significant bit of Out2 bus
Scale width of input bus
Most ⁽¹⁾ significant bit of Out1 bus
Least ⁽¹⁾ significant bit of Out1 bus
Most ⁽¹⁾ significant bit of Out2 bus
Least ⁽¹⁾ significant bit of Out2 bus
Utility Bus Split Register Descriptions
There are no registers in this core.
Utility Bus Split Interrupt Descriptions
There are no interrupts associated with this core.
Utility Bus Split Block Diagram
The Utility Bus Split block diagram is shown in Figure 2.
X-Ref Target - Figure 2
Input Bus
[0 : C_SIZE_IN-1]
Output Bus 1
[C_LEFT_POS : C_SPLIT-1]
Output Bus 2
[C_SPLIT : C_SIZE_IN-1]
DS481_02_100609
Figure 2: Utility Bus Split Block Diagram
DS484 December 2, 2009
www.xilinx.com
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Product Specification