DS484 Datasheet, PDF (1/5 Pages) Xilinx, Inc – The Split Operation has the following features:

Utility Bus Split (v1.00a)
DS484 December 2, 2009
Product Specification
Introduction
The Utility Bus Split core splits a bus into smaller buses
using the Xilinx Platform Studio (XPS).
The core splits one input bus into two output buses
which serve as glue logic between peripherals.
Features
• The Split Operation has the following features:
♦ Configurable size of the input and output
vectors
LogiCORE™ IP Facts
Core Specifics
Supported Device
Family
Spartan^®-3A/3A DSP, Spartan-3,
Spartan-3E, Automotive
Spartan 3/3E/3A/3A DSP, Spartan-6,
Virtex^®-4 /4Q/4QV, Virtex-5/5FX,
Virtex-6/6CX
Resources Used
Not Applicable
Provided with Core
Documentation
Product Specification
Design File Formats VHDL
Constraints File
EDK TCL Generated
Verification
N/A
Instantiation Template EDK
Design Tool Requirements
Xilinx Implementation
Tools
ISE® 11.4 or later
Verification
ModelSim PE/SE 6.4b or later
Simulation
ModelSim PE/SE 6.4b or later
Synthesis
XST
Support
Provided by Xilinx, Inc.
© 2003-2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. All other trademarks are the property of their respective owners.
DS484 December 2, 2009
www.xilinx.com
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Product Specification