DS482 Datasheet, PDF (4/5 Pages) Xilinx, Inc – Utility Reduced Logic

Utility Reduced Logic (v1.00a)
Device Utilization and Performance Benchmarks
Table 4: Utility Reduced Logic Resource Utilization
Parameters
Resources
Flip-Flops
4-input LUTs
C_SIZE = 2
0
1
C_SIZE = 8
0
3
C_SIZE = 16
0
9
C_SIZE = 32
0
11
There are no performance benchmarks available.
Specification Exceptions
Not applicable
Reference Documents
None
Support
Xilinx provides technical support for this LogiCORE product when used as described in the product
documentation. Xilinx cannot guarantee timing, functionality, or support of product if implemented in
devices that are not defined in the documentation, if customized beyond that allowed in the product
documentation, or if changes are made to any section of the design labeled DO NOT MODIFY.
Revision History
Date
3/28/03
12/19/03
7/15/04
8/17/04
9/22/04
4/24/09
12/2/09
Version
1.0
1.1
1.2
1.3
1.4
1.5
1.6
Description of Revisions
Revision History added to document.
Added LogiCORE Facts table. Reformatted to current Xilinx template.
Minor corrections and updates.
Updated for EDK 6.3. Updated trademarks and supported family device listing.
Updated to use new data sheet template.
Replaced references to supported device families and tool names with hyperlink to
PDF file.
Listed supported devices families in LogiCORE Table; added Spartan-6 and Virtex-
6 support, converted to new DS template.
4
www.xilinx.com
DS482 December 2, 2009
Product Specification