DS482 Datasheet, PDF (2/5 Pages) Xilinx, Inc – Utility Reduced Logic

Utility Reduced Logic (v1.00a)
Functional Description
Figure 1 shows a Utility Reduced Logic in a system.
X-Ref Target - Figure 1
Peripheral 1
Peripheral 3
Peripheral 2
f
Utility Reduced
Logic
DS482_01_100709
Figure 1: Utility Reduced Logic in a System
Utility Reduced Logic Parameters
Table 1: Utility Reduced Logic Parameters
Parameter
Description
C_SIZE
C_OPERATION
The vector size of input bus. Minimum value is 2.
f The vector operation to perform. The supported functions ( ) are:
“and”, “or”, “xor”
Allowable Parameter Combinations
There are no restrictions on allowed parameter combinations for this core.
Utility Reduced Logic I/O Signals
Type
Integer
String
Table 2: Utility Reduced Logic I/O Signals
Signal Interface I/O
Description
Op1
None
I
Input bus [0 : C_SIZE-1]
Res
None
O One bit output signal. Result from the reduced logic operation.
2
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DS482 December 2, 2009
Product Specification