DS482 Datasheet, PDF (3/5 Pages) Xilinx, Inc – Utility Reduced Logic

Utility Reduced Logic (v1.00a)
Parameter-Port Dependencies
Table 3: Port and Parameter Dependencies
Name
Affects
Depends
Design Parameters
C_SIZE
Op1
0 to C_SIZE-1
Port Signals
Op1
C_SIZE
Relationship Description
Scale width of input bus
Scale width of input bus
Utility Reduced Logic Register Descriptions
There are no registers in this core.
Utility Reduced Logic Interrupt Descriptions
There are no interrupts associated with this core.
Utility Reduced Logic Block Diagram
The Utility Reduced Logic block diagram is shown in Figure 2.
X-Ref Target - Figure 2
Op1 (0:CSIZE-1)
f
Res
DS482_02_100709
Figure 2: Utility Reduced Logic Block Diagram
Design Implementation
Design Tools
The Utility Reduced Logic design is handwritten.
Xilinx XST is the synthesis tool used for synthesizing the Reduced Logic device.
Target Technology
The target technology is an FPGA listed in Supported Device Family field of the LogiCORE IP Facts
Table.
DS482 December 2, 2009
www.xilinx.com
3
Product Specification